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57 Some bug fixes to the dhrystone benchmark, and some compile time defines for
the test bench processor. Of the most important note is the fix to detect
lockups on the debug/wishbone bus--that has been a real help in getting the
ZipCPU installed and the debugger working on the various boards I'm working
with. (i.e., it's helped me find and figure out why/when things haven't worked)
Of other note is the new 'G' key in the testbench code, to cause the test
bench to run without user interaction until the next keystroke. This is
very valuable in long programs, as it makes getting to/from breakpoints
easier (i.e. you don't have to wait as long, hit 'G', breathe, hit 'space'
and you're there).
dgisselq 3204d 09h /
56 Here's a bit of work in progress for getting the Zip CPU working on a XuLA2
board. Many changes include: the existence of a cpudefs.v file to control
what "options" are included in the ZipCPU build. This allows build control
to be separated from the project directory (one build for a XuLA2 board,
another for a Basys-3 development board). Other changes have made things
perhaps harder to read, but they get rid of warnings from XST.

A big change was the addition of the (* ram_style="distributed" *) comment
for the register set. This was necessary to keep XST from inferring a block
RAM and breaking the logic that was supposed to take place between a register
read and when it was used.
dgisselq 3204d 09h /
55 A test was added to double check whether carry following right shifts worked.
This was a necessary part of getting two cycle linear feedback shift register
operations working for a memory test on a XuLA2 board. With this, I can now
verify that such feedback registers work for pseudorandom number purposes.
dgisselq 3204d 09h /
54 This builds on the support for backslash character escapes in both single
and multicharacter expressions. Backslash character escapes are now
possible with quotations and backslashes, and the same code to interpret
the escapes is applied to both single and multicharacter sequences.
dgisselq 3204d 09h /
53 Updated the #include/#define directives to work properly for nested includes.
(They were supposed to work properly for nested includes before ... and didn't)
This fixes those bugs.
dgisselq 3204d 09h /
52 Added the capability to "see" character's encoded within a binary file,
by printing the character value(s) of each opcode (if they are printable)
on each line.
dgisselq 3204d 09h /
51 Added the capability to look at binary files and 'see' characters as they
are encoded in memory.
dgisselq 3204d 09h /
50 Dhrystone benchmark updates--added the copyright notice. (Oops!) dgisselq 3214d 00h /
49 Final set of changes finishing the Dhrystone package. Dhrystone, as
implemented by hand in assembly, now works.
dgisselq 3214d 00h /
48 Files added/updated to get Dhrystone benchmark to work. Several fixes
to the CPU in the process, 'cause it wasn't working. Stall-less ALU
ops now work better, to include grabbing the memory result as it comes out
of the memory unit and placing it straight into either ALU or memory unit
for the next instruction.
dgisselq 3214d 00h /
47 Added some new graphics, includes the file for the Zip Bones system. dgisselq 3214d 00h /
46 A series of updates associated with getting Dhrystone to work. Includes
updates to getting multiple files to link/work together within the assembler,
as well as getting quoted quotations to work in the lexer, and better
include file support in the preprocessor.
dgisselq 3214d 00h /
45 Library routines for 32-bit multiply and divide, both signed and unsigned. dgisselq 3214d 00h /
44 ?? dgisselq 3214d 01h /
43 Minor edits to the C++ testbench. dgisselq 3214d 01h /
42 Oops -- forgot to add the stack. dgisselq 3214d 01h /
41 Assembly file for the Dhrystone benchmark added. dgisselq 3214d 01h /
40 Quick update, updates the assembly for the new version of the assembler. dgisselq 3214d 01h /
39 Here's the documentation update to support the pipelined read/writes of
the bus from the CPU, as well as the test file that proved they worked.
dgisselq 3217d 03h /
38 A couple of quick updates:

- The Zip CPU now supports pipelined memory access at one clock per
instruction (assuming all the instructions are in the cache)
- There is now a 'zipbones' module to build a Zip System without peripherals.
Any peripherals would then need to be external to the CPU.
- Some bug fixes.

Documentation changes coming shortly.
dgisselq 3217d 06h /

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