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65 Lots of logic simplifications to the core, in addition to better support for
illegal instruction detection and bus error detection. The biggest change
had to deal with pushing the debug write interface into the ALU write
processing path. This simplifies the logic of adjusting the PC and CC
registers primarily, but also any writes to other registers. It also delays
these register writes by a clock, but since the debug interface is already
ridiculously slow I doubt that matters any.
dgisselq 2656d 04h /
64 Shuffled some comments into here from elsewhere. dgisselq 2656d 04h /
63 Simplified bus interactions, and added support for detecting illegal
instructions (i.e. bus errors) in the pipefetch routine.
dgisselq 2656d 04h /
62 Simplified the subtraction logic, so the carry bit no longer depends on
a separate 32-bit operation but becomes part of the subtract operation.
dgisselq 2656d 04h /
61 Simplified the bus delay logic. Depends upon the stall line being irrelevant
outside of a bus cycle.
dgisselq 2656d 04h /
60 Fixed assembler processing of jump instructions, so that the new fast
return instruction can be used. The test file was modified to test
pipelined value passing within the CPU. That's where the value gets
(re)used before being stored back in the register file. As of this release,
all tests work.
dgisselq 2656d 04h /
59 Adjusted these library routines to use the new stack frame and calling
conventions.
dgisselq 2656d 04h /
58 Added a rudimentary profiling support to the simulator. dgisselq 2656d 04h /
57 Some bug fixes to the dhrystone benchmark, and some compile time defines for
the test bench processor. Of the most important note is the fix to detect
lockups on the debug/wishbone bus--that has been a real help in getting the
ZipCPU installed and the debugger working on the various boards I'm working
with. (i.e., it's helped me find and figure out why/when things haven't worked)
Of other note is the new 'G' key in the testbench code, to cause the test
bench to run without user interaction until the next keystroke. This is
very valuable in long programs, as it makes getting to/from breakpoints
easier (i.e. you don't have to wait as long, hit 'G', breathe, hit 'space'
and you're there).
dgisselq 2666d 06h /
56 Here's a bit of work in progress for getting the Zip CPU working on a XuLA2
board. Many changes include: the existence of a cpudefs.v file to control
what "options" are included in the ZipCPU build. This allows build control
to be separated from the project directory (one build for a XuLA2 board,
another for a Basys-3 development board). Other changes have made things
perhaps harder to read, but they get rid of warnings from XST.

A big change was the addition of the (* ram_style="distributed" *) comment
for the register set. This was necessary to keep XST from inferring a block
RAM and breaking the logic that was supposed to take place between a register
read and when it was used.
dgisselq 2666d 06h /

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