| Rev |
Log message |
Author |
Age |
Path |
| 86 |
Removed the requirement to have the dev.scope.cpu hardware defined outside
of the Zip CPU (it was defined in another project). This was causing a bus
error in the simulator (which it should have), but taking it out fixes things
in the simulator (while removing capability from one special piece of H/W). |
dgisselq |
3028d 22h |
/ |
| 85 |
Minor update/correction to operand B definition. |
dgisselq |
3028d 22h |
/ |
| 84 |
Minor updates. |
dgisselq |
3028d 22h |
/ |
| 83 |
Added a flag to indicate whether an exception took place on the first
or second half of a VLIW instruction--will be zero in non-VLIW mode,
equivalent to the second half of the instruction having caused the
exception. (Expect these flags to be reordered some time in the future into
a less haphazard ordering ...)
Vastly simplified the pipeline logic, primarily for op_stall, but also touched
opA and opB. (Trying to fit within timing on Spartan 6 ...)
Changed division instruction to include a reset on clear_pipeline, to make
certain [BC $addr; DIV Rx,Ry ] works regardless of whether the condition is
true. |
dgisselq |
3028d 22h |
/ |
| 82 |
Found and (I hope) fixed a nasty bug that would send the prefetch into an
endless loop whenever you jumped to an instruction at the last location
in an unloaded cache line. |
dgisselq |
3028d 22h |
/ |
| 81 |
Trying to clean up ISE generated warnings. |
dgisselq |
3028d 22h |
/ |
| 80 |
Bug fix: declared the (combined) multiply to be signed again. Also
changed the name of the generate'd for block, to keep ISE from complaining. |
dgisselq |
3028d 22h |
/ |
| 79 |
Adjusted the opcodes for NOOP, BREAK, and LOCK. |
dgisselq |
3033d 02h |
/ |
| 78 |
Found/corrected annoying bug in floating point documentation of the opcode
table. |
dgisselq |
3033d 02h |
/ |
| 77 |
First check-in: the test bench for the divide instruction. |
dgisselq |
3034d 01h |
/ |
| 76 |
The biggest change here was to zippy_tb, to make it more similar to the debugger
and to make it work with VLIW-type instructions. |
dgisselq |
3034d 01h |
/ |
| 75 |
Modified for VLIW instructions. |
dgisselq |
3034d 01h |
/ |
| 74 |
Added a bunch of debugging code to the Dhrystone benchmark assembly file, as
well as two new testing assembly files. |
dgisselq |
3034d 01h |
/ |
| 73 |
Documentations updates. |
dgisselq |
3034d 01h |
/ |
| 72 |
Some updated graphics, now containing images of the CPU that include the
divide and (currently non-existant) floating point unit. |
dgisselq |
3034d 01h |
/ |
| 71 |
This contains a bunch of bug fixes. (A lot ...) For example, the pipeline
stall code has also seriously changed, to fixed the pipeline memory load/op
stage conflict, while maintaining no-stall operation for operands that don't
need an offset. This had a cascading effect, however, so that the multiply
could no longer complete in a single cycle. Therefore, the timing on the
multiplies was slowed down to two cycles from a single cycle. (It's the
only two-cycle ALU operation ...) The illegal instruction code has also been
fixed, so that illegal instructions no longer stalls the prefetch bus. |
dgisselq |
3034d 01h |
/ |
| 70 |
Updated the assembler support files, zopcodes in particular, to handle
the disassembly of the new very long instruction word codes. |
dgisselq |
3034d 01h |
/ |
| 69 |
This implements the "new Instruction Set" architecture for the Zip CPU. It's
a massive change set, that touches just about everything but probably not
enough of everything. Please see the spec.pdf for a description of this
new architecture. |
dgisselq |
3040d 06h |
/ |
| 68 |
Updated specification, includes well illustrated pipeline discussion. |
dgisselq |
3075d 06h |
/ |
| 67 |
Includes timing diagrams in support of a very descriptive specification section. |
dgisselq |
3075d 06h |
/ |
| 66 |
Adjusted the support for the DEBUG_SCOPE within these so that it can be
compiled in, or not, based upon an external build configuration file: cpudefs.v.
That allows me to make that file project specific, while the rest of the CPU
is shared among all projects. |
dgisselq |
3101d 06h |
/ |
| 65 |
Lots of logic simplifications to the core, in addition to better support for
illegal instruction detection and bus error detection. The biggest change
had to deal with pushing the debug write interface into the ALU write
processing path. This simplifies the logic of adjusting the PC and CC
registers primarily, but also any writes to other registers. It also delays
these register writes by a clock, but since the debug interface is already
ridiculously slow I doubt that matters any. |
dgisselq |
3101d 06h |
/ |
| 64 |
Shuffled some comments into here from elsewhere. |
dgisselq |
3101d 06h |
/ |
| 63 |
Simplified bus interactions, and added support for detecting illegal
instructions (i.e. bus errors) in the pipefetch routine. |
dgisselq |
3101d 06h |
/ |
| 62 |
Simplified the subtraction logic, so the carry bit no longer depends on
a separate 32-bit operation but becomes part of the subtract operation. |
dgisselq |
3101d 06h |
/ |
| 61 |
Simplified the bus delay logic. Depends upon the stall line being irrelevant
outside of a bus cycle. |
dgisselq |
3101d 06h |
/ |
| 60 |
Fixed assembler processing of jump instructions, so that the new fast
return instruction can be used. The test file was modified to test
pipelined value passing within the CPU. That's where the value gets
(re)used before being stored back in the register file. As of this release,
all tests work. |
dgisselq |
3101d 06h |
/ |
| 59 |
Adjusted these library routines to use the new stack frame and calling
conventions. |
dgisselq |
3101d 06h |
/ |
| 58 |
Added a rudimentary profiling support to the simulator. |
dgisselq |
3101d 06h |
/ |
| 57 |
Some bug fixes to the dhrystone benchmark, and some compile time defines for
the test bench processor. Of the most important note is the fix to detect
lockups on the debug/wishbone bus--that has been a real help in getting the
ZipCPU installed and the debugger working on the various boards I'm working
with. (i.e., it's helped me find and figure out why/when things haven't worked)
Of other note is the new 'G' key in the testbench code, to cause the test
bench to run without user interaction until the next keystroke. This is
very valuable in long programs, as it makes getting to/from breakpoints
easier (i.e. you don't have to wait as long, hit 'G', breathe, hit 'space'
and you're there). |
dgisselq |
3111d 08h |
/ |
