URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

[/] [zipcpu/] - Rev 101

Rev	Log message	Author	Age	Path
81	Trying to clean up ISE generated warnings.	dgisselq	3028d 01h	/zipcpu/
80	Bug fix: declared the (combined) multiply to be signed again. Also changed the name of the generate'd for block, to keep ISE from complaining.	dgisselq	3028d 01h	/zipcpu/
79	Adjusted the opcodes for NOOP, BREAK, and LOCK.	dgisselq	3032d 04h	/zipcpu/
78	Found/corrected annoying bug in floating point documentation of the opcode table.	dgisselq	3032d 05h	/zipcpu/
77	First check-in: the test bench for the divide instruction.	dgisselq	3033d 04h	/zipcpu/
76	The biggest change here was to zippy_tb, to make it more similar to the debugger and to make it work with VLIW-type instructions.	dgisselq	3033d 04h	/zipcpu/
75	Modified for VLIW instructions.	dgisselq	3033d 04h	/zipcpu/
74	Added a bunch of debugging code to the Dhrystone benchmark assembly file, as well as two new testing assembly files.	dgisselq	3033d 04h	/zipcpu/
73	Documentations updates.	dgisselq	3033d 04h	/zipcpu/
72	Some updated graphics, now containing images of the CPU that include the divide and (currently non-existant) floating point unit.	dgisselq	3033d 04h	/zipcpu/