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[/] [zipcpu/] - Rev 105

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105 Fixed some nasty early branching bugs. Adjusted the Makefile to declare that
cpudefs.h was automatically generated from cpudefs.v, and made sure that
zipbones included the cpudefs.v so it could get the DEBUG_SCOPE define.
In addition, the test.S was updated to test long jumps, the early branching
bug we found, and all three early branching instructions: ADD #x,PC, LOC(PC),PC,
and LDI #x,PC.
dgisselq 2395d 04h /zipcpu/
104 An updated build script, actually builds zip-gcc. dgisselq 2396d 05h /zipcpu/
103 A barely functional, but somewhat working, version of GCC to check in.
If the Lord is willing, it should be accompanied by a newlib port soon.
That port should move the GCC status from barely functional but somewhat
working to functional and working, although not (yet) complete.
dgisselq 2396d 09h /zipcpu/
102 Updated bugfix version of the binutils patch, and a first patch of GCC.
The GCC patch is undergoing ongoing and active development. It is also known to
continue to contain active bugs. (It's not done yet.)
dgisselq 2398d 18h /zipcpu/
101 Adjusted the "BREAK" instruction so that it will now disassemble properly
with an operand. This was necessary to create a (trap_if ...) instruction
for the GCC compiler.
dgisselq 2400d 20h /zipcpu/
100 Some changes to support early branching: branches are now ADD #x,PC instructions
instead of MOV #x(PC),PC--providing greater range to the CPU. When that range
is insufficient, ZPARSER now recognizes long jump instructions coded as
LOD (PC),PC followed by the jump address. (This change was made necessary by
the need to build an assembler/linker that could create instructions that would
jump to any address in the 32-bit address space. In short, a part of the
ongoing GCC upgrade and rework.)
dgisselq 2400d 20h /zipcpu/
99 Added big-endian versus little-endian functionality. You can now specify which
your input file is as a command line parameter, and zdump will properly
disassemble the file.
dgisselq 2400d 21h /zipcpu/
98 Added justed longjump instructions from the previous (not used, broken)
functionality to the new LOD (PC),PC functionality.
dgisselq 2400d 21h /zipcpu/
97 Added longjump instructions. dgisselq 2400d 21h /zipcpu/
96 Added the longjump functionality, so that the assembler will properly assemble
instructions to arbitrary 32-bit addresses.
dgisselq 2400d 21h /zipcpu/
95 Fixed a bug whereby a mistaken code for CLR was masking a valid LDI of a large
integer value.
dgisselq 2403d 03h /zipcpu/
94 These changes make it possible to build binutils-2.25/ here in this
directory. "make binutils" should be all that is necessary to build the
entire binutils package for the Zip CPU.

The default configure script, run from gas-script.sh below, will build and
install these utilities in an install/ subdirectory made below sw/.
dgisselq 2428d 00h /zipcpu/
93 A BINUTILS BACKEND IS NOW AVAILABLE!!!! dgisselq 2435d 22h /zipcpu/
92 Adjustments made to match the simplified early branching. dgisselq 2435d 22h /zipcpu/
91 Minor updates. dgisselq 2435d 22h /zipcpu/
90 Removed MOV x(PC),PC from the list of possible early branching instructions.
ADD X,PC and LDI X,PC are now the only recognized early branching instructions.
This was done to spare logic, although I don't think I spared more than a
LUT or two.
dgisselq 2435d 22h /zipcpu/
89 Minor changes, to include making default branching an ADD.[condition] X,PC
instruction, rather than allowing both MOV X(PC),PC and ADD X,PC instructions.

Further zopcodes.cpp contains several bug fixes.
dgisselq 2435d 22h /zipcpu/
88 Eliminated some warnings. The div fixes were to simplify the logic, even though
the result is less readable ...
dgisselq 2459d 21h /zipcpu/
87 Adjusted the operator input line to reflect actual logic inputs, rather
than the registered inputs which may have been out of date. (Indeed, they
were out of date for the bug I was chasing and fixed ...)
dgisselq 2461d 20h /zipcpu/
86 Removed the requirement to have the dev.scope.cpu hardware defined outside
of the Zip CPU (it was defined in another project). This was causing a bus
error in the simulator (which it should have), but taking it out fixes things
in the simulator (while removing capability from one special piece of H/W).
dgisselq 2461d 20h /zipcpu/

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