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Rev Log message Author Age Path
109 This file is now marked as obsolete. dgisselq 3040d 03h /zipcpu/
108 Just to clarify expectations ... this makefile hardly builds anything. dgisselq 3050d 04h /zipcpu/
107 Adding a missing file. dgisselq 3050d 20h /zipcpu/
106 Updated to allow building without the sources for the graphics used in the
document.
dgisselq 3050d 23h /zipcpu/
105 Fixed some nasty early branching bugs. Adjusted the Makefile to declare that
cpudefs.h was automatically generated from cpudefs.v, and made sure that
zipbones included the cpudefs.v so it could get the DEBUG_SCOPE define.
In addition, the test.S was updated to test long jumps, the early branching
bug we found, and all three early branching instructions: ADD #x,PC, LOC(PC),PC,
and LDI #x,PC.
dgisselq 3056d 03h /zipcpu/
104 An updated build script, actually builds zip-gcc. dgisselq 3057d 03h /zipcpu/
103 A barely functional, but somewhat working, version of GCC to check in.
If the Lord is willing, it should be accompanied by a newlib port soon.
That port should move the GCC status from barely functional but somewhat
working to functional and working, although not (yet) complete.
dgisselq 3057d 08h /zipcpu/
102 Updated bugfix version of the binutils patch, and a first patch of GCC.
The GCC patch is undergoing ongoing and active development. It is also known to
continue to contain active bugs. (It's not done yet.)
dgisselq 3059d 16h /zipcpu/
101 Adjusted the "BREAK" instruction so that it will now disassemble properly
with an operand. This was necessary to create a (trap_if ...) instruction
for the GCC compiler.
dgisselq 3061d 19h /zipcpu/
100 Some changes to support early branching: branches are now ADD #x,PC instructions
instead of MOV #x(PC),PC--providing greater range to the CPU. When that range
is insufficient, ZPARSER now recognizes long jump instructions coded as
LOD (PC),PC followed by the jump address. (This change was made necessary by
the need to build an assembler/linker that could create instructions that would
jump to any address in the 32-bit address space. In short, a part of the
ongoing GCC upgrade and rework.)
dgisselq 3061d 19h /zipcpu/
99 Added big-endian versus little-endian functionality. You can now specify which
your input file is as a command line parameter, and zdump will properly
disassemble the file.
dgisselq 3061d 19h /zipcpu/
98 Added justed longjump instructions from the previous (not used, broken)
functionality to the new LOD (PC),PC functionality.
dgisselq 3061d 19h /zipcpu/
97 Added longjump instructions. dgisselq 3061d 19h /zipcpu/
96 Added the longjump functionality, so that the assembler will properly assemble
instructions to arbitrary 32-bit addresses.
dgisselq 3061d 19h /zipcpu/
95 Fixed a bug whereby a mistaken code for CLR was masking a valid LDI of a large
integer value.
dgisselq 3064d 01h /zipcpu/
94 These changes make it possible to build binutils-2.25/ here in this
directory. "make binutils" should be all that is necessary to build the
entire binutils package for the Zip CPU.

The default configure script, run from gas-script.sh below, will build and
install these utilities in an install/ subdirectory made below sw/.
dgisselq 3088d 22h /zipcpu/
93 A BINUTILS BACKEND IS NOW AVAILABLE!!!! dgisselq 3096d 20h /zipcpu/
92 Adjustments made to match the simplified early branching. dgisselq 3096d 20h /zipcpu/
91 Minor updates. dgisselq 3096d 20h /zipcpu/
90 Removed MOV x(PC),PC from the list of possible early branching instructions.
ADD X,PC and LDI X,PC are now the only recognized early branching instructions.
This was done to spare logic, although I don't think I spared more than a
LUT or two.
dgisselq 3096d 20h /zipcpu/
89 Minor changes, to include making default branching an ADD.[condition] X,PC
instruction, rather than allowing both MOV X(PC),PC and ADD X,PC instructions.

Further zopcodes.cpp contains several bug fixes.
dgisselq 3096d 20h /zipcpu/
88 Eliminated some warnings. The div fixes were to simplify the logic, even though
the result is less readable ...
dgisselq 3120d 20h /zipcpu/
87 Adjusted the operator input line to reflect actual logic inputs, rather
than the registered inputs which may have been out of date. (Indeed, they
were out of date for the bug I was chasing and fixed ...)
dgisselq 3122d 18h /zipcpu/
86 Removed the requirement to have the dev.scope.cpu hardware defined outside
of the Zip CPU (it was defined in another project). This was causing a bus
error in the simulator (which it should have), but taking it out fixes things
in the simulator (while removing capability from one special piece of H/W).
dgisselq 3122d 18h /zipcpu/
85 Minor update/correction to operand B definition. dgisselq 3122d 18h /zipcpu/
84 Minor updates. dgisselq 3122d 18h /zipcpu/
83 Added a flag to indicate whether an exception took place on the first
or second half of a VLIW instruction--will be zero in non-VLIW mode,
equivalent to the second half of the instruction having caused the
exception. (Expect these flags to be reordered some time in the future into
a less haphazard ordering ...)

Vastly simplified the pipeline logic, primarily for op_stall, but also touched
opA and opB. (Trying to fit within timing on Spartan 6 ...)

Changed division instruction to include a reset on clear_pipeline, to make
certain [BC $addr; DIV Rx,Ry ] works regardless of whether the condition is
true.
dgisselq 3122d 18h /zipcpu/
82 Found and (I hope) fixed a nasty bug that would send the prefetch into an
endless loop whenever you jumped to an instruction at the last location
in an unloaded cache line.
dgisselq 3122d 19h /zipcpu/
81 Trying to clean up ISE generated warnings. dgisselq 3122d 19h /zipcpu/
80 Bug fix: declared the (combined) multiply to be signed again. Also
changed the name of the generate'd for block, to keep ISE from complaining.
dgisselq 3122d 19h /zipcpu/

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