| Rev |
Log message |
Author |
Age |
Path |
| 193 |
These changes make it so the ALU multiplies pass a test-bench. |
dgisselq |
2723d 18h |
/zipcpu/ |
| 192 |
Fixed a bug with constant alignment in the assembler. |
dgisselq |
2723d 18h |
/zipcpu/ |
| 191 |
Updated toolchain, more information on the example debugger. |
dgisselq |
2738d 21h |
/zipcpu/ |
| 190 |
Added the copyright statement back in. |
dgisselq |
2740d 13h |
/zipcpu/ |
| 189 |
Final, as delivered, ORCONF slides. |
dgisselq |
2740d 13h |
/zipcpu/ |
| 188 |
Adjusted the opcodes to match the binutils port: added RTN instructions, and
allowed BREAK instructions to include an immediate--to be interpreted by the
debugger. |
dgisselq |
2772d 15h |
/zipcpu/ |
| 187 |
Updated to match changed register definitions within the core. |
dgisselq |
2772d 15h |
/zipcpu/ |
| 186 |
Now allows profile dumping for ELF executables. |
dgisselq |
2772d 15h |
/zipcpu/ |
| 185 |
Now includes the proper flags for building with ELF executable file support. |
dgisselq |
2772d 15h |
/zipcpu/ |
| 184 |
Adjusted the illegal instruction option documentation. |
dgisselq |
2772d 15h |
/zipcpu/ |
| 183 |
Cleaned up the system so that !CYC implies !STB as well. |
dgisselq |
2772d 15h |
/zipcpu/ |
| 182 |
Bug fix for fast memories. This now works for memories with single cycle
latencies. |
dgisselq |
2772d 15h |
/zipcpu/ |
| 181 |
Adjusted the wishbone logic to include our wishbone simplification that if
CYC is ever low, STB must be low as well. |
dgisselq |
2772d 16h |
/zipcpu/ |
| 180 |
Cleaned up the stall logic--made it independent of whether or not we are
designed to be alternating or not. |
dgisselq |
2772d 16h |
/zipcpu/ |
| 179 |
Lots of changes, most (all?) of them to the non-pipelined core. The resulting
core is now about 100-120 LUTs smaller when not-pipelined, and yet maintains
the pipelined logic when necessary. |
dgisselq |
2772d 16h |
/zipcpu/ |
| 178 |
Rewrote the parameter controlled logic to be just that: perameter controller,
rather than depending upon generics. The result reduces our area by a couple
LUTs. |
dgisselq |
2772d 16h |
/zipcpu/ |
| 177 |
Fixed the illegal address logic to be more precise. |
dgisselq |
2772d 16h |
/zipcpu/ |
| 176 |
Switched from distributed to block RAM, and adjusted the logic to help
timing closure. The resulting core will build in designs up to 200MHz in
speed. |
dgisselq |
2772d 16h |
/zipcpu/ |
| 175 |
Fixed the carry bit for logical shifts: it is the last bit shifted out of the
register. 0x80000000>>32 yields a 0 with carry set. Anything logically
shifted by a number greater than thirty two clears carry and register. |
dgisselq |
2772d 16h |
/zipcpu/ |
| 174 |
Simplified the divide to improve timing performance. |
dgisselq |
2772d 16h |
/zipcpu/ |
| 173 |
Adjusted the pdfinfo field, to accommodate Google's bot. |
dgisselq |
2772d 16h |
/zipcpu/ |
| 172 |
Added a test to see if the compiler properly handles a large number of
arguments. Further, the sibcall enabled compiler now correcly makes a
sibcall from the end of txreg(). |
dgisselq |
2772d 16h |
/zipcpu/ |
| 171 |
This fixes the problem whereby the ZipCPU didn't properly access more than
5 word-sized function parameters. |
dgisselq |
2774d 21h |
/zipcpu/ |
| 170 |
Minor updates to the orconf.pdf pre-conference slide. (Added the 'to be
revealed' line. |
dgisselq |
2784d 15h |
/zipcpu/ |
| 169 |
Added details of LM32 to the (pre) ORConf survey slide in trunk/doc. |
dgisselq |
2820d 16h |
/zipcpu/ |
| 168 |
An updated version of the intensive CPU test. This one runs from C, and
requires a UART port and a PIC, but can run quite successfully on multiple
SoCs that have been built with the ZipCPU internal to them. |
dgisselq |
2833d 15h |
/zipcpu/ |
| 167 |
Updated the spec to reflect changes in the CC register: the user break
flag, and the ability to command a clearing of the instruction cache. |
dgisselq |
2833d 15h |
/zipcpu/ |
| 166 |
Bugfix version. This fixes a problem whereby function addresses with offsets
were not properly calculated, together with properly setting up pcrelative
offsets when using the move function together with a label. |
dgisselq |
2833d 20h |
/zipcpu/ |
| 165 |
Added a test to make certain that the arithmetic right shift was properly
propagating the high order bit. (The test works under verilator, but didn't
initially work in Xilinx -- thus a difference between the two.) |
dgisselq |
2833d 20h |
/zipcpu/ |
| 164 |
Updated with inputs from Hellwig Geisse regarding the details of the ECO32
CPU. |
dgisselq |
2841d 21h |
/zipcpu/ |
