URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

[/] [zipcpu/] - Rev 198

Rev	Log message	Author	Age	Path
178	Rewrote the parameter controlled logic to be just that: perameter controller, rather than depending upon generics. The result reduces our area by a couple LUTs.	dgisselq	2778d 05h	/zipcpu/
177	Fixed the illegal address logic to be more precise.	dgisselq	2778d 05h	/zipcpu/
176	Switched from distributed to block RAM, and adjusted the logic to help timing closure. The resulting core will build in designs up to 200MHz in speed.	dgisselq	2778d 05h	/zipcpu/
175	Fixed the carry bit for logical shifts: it is the last bit shifted out of the register. 0x80000000>>32 yields a 0 with carry set. Anything logically shifted by a number greater than thirty two clears carry and register.	dgisselq	2778d 05h	/zipcpu/
174	Simplified the divide to improve timing performance.	dgisselq	2778d 05h	/zipcpu/
173	Adjusted the pdfinfo field, to accommodate Google's bot.	dgisselq	2778d 05h	/zipcpu/
172	Added a test to see if the compiler properly handles a large number of arguments. Further, the sibcall enabled compiler now correcly makes a sibcall from the end of txreg().	dgisselq	2778d 05h	/zipcpu/
171	This fixes the problem whereby the ZipCPU didn't properly access more than 5 word-sized function parameters.	dgisselq	2780d 11h	/zipcpu/
170	Minor updates to the orconf.pdf pre-conference slide. (Added the 'to be revealed' line.	dgisselq	2790d 05h	/zipcpu/
169	Added details of LM32 to the (pre) ORConf survey slide in trunk/doc.	dgisselq	2826d 05h	/zipcpu/