| Rev |
Log message |
Author |
Age |
Path |
| 205 |
Updating core to current/best version, to include dblfetch support and full CIS support |
dgisselq |
2578d 11h |
/zipcpu/ |
| 204 |
Added the two simulators back into the SVN repository |
dgisselq |
2597d 07h |
/zipcpu/ |
| 203 |
Removed the (now unused) old GCC compiler, v5.3.0 |
dgisselq |
2597d 07h |
/zipcpu/ |
| 202 |
Additional ZipCPU changes associated w 8b upgrade |
dgisselq |
2597d 08h |
/zipcpu/ |
| 201 |
RTL files for the 8-bit capable ZipCPU. |
dgisselq |
2597d 09h |
/zipcpu/ |
| 200 |
Lots of GCC bugs fixed, some new features added, longs should work now. The
build scripts have also been updated and simplified. |
dgisselq |
2696d 15h |
/zipcpu/ |
| 199 |
Massive specification rewrite, brings it up to date with the current ZipCPU
state. This does not reflect any major change to the CPU. |
dgisselq |
2722d 04h |
/zipcpu/ |
| 198 |
Added a copyright notice. |
dgisselq |
2723d 08h |
/zipcpu/ |
| 197 |
Added a new multiply testbench. Other changes were necessary to follow. |
dgisselq |
2723d 08h |
/zipcpu/ |
| 196 |
Updated internal documentation. |
dgisselq |
2723d 08h |
/zipcpu/ |
| 195 |
Adds a new mode that can handle a delayed stall signal. |
dgisselq |
2723d 08h |
/zipcpu/ |
| 194 |
Cleaned up some parameters, trying to create more consistency. |
dgisselq |
2723d 08h |
/zipcpu/ |
| 193 |
These changes make it so the ALU multiplies pass a test-bench. |
dgisselq |
2723d 08h |
/zipcpu/ |
| 192 |
Fixed a bug with constant alignment in the assembler. |
dgisselq |
2723d 08h |
/zipcpu/ |
| 191 |
Updated toolchain, more information on the example debugger. |
dgisselq |
2738d 12h |
/zipcpu/ |
| 190 |
Added the copyright statement back in. |
dgisselq |
2740d 03h |
/zipcpu/ |
| 189 |
Final, as delivered, ORCONF slides. |
dgisselq |
2740d 03h |
/zipcpu/ |
| 188 |
Adjusted the opcodes to match the binutils port: added RTN instructions, and
allowed BREAK instructions to include an immediate--to be interpreted by the
debugger. |
dgisselq |
2772d 06h |
/zipcpu/ |
| 187 |
Updated to match changed register definitions within the core. |
dgisselq |
2772d 06h |
/zipcpu/ |
| 186 |
Now allows profile dumping for ELF executables. |
dgisselq |
2772d 06h |
/zipcpu/ |
| 185 |
Now includes the proper flags for building with ELF executable file support. |
dgisselq |
2772d 06h |
/zipcpu/ |
| 184 |
Adjusted the illegal instruction option documentation. |
dgisselq |
2772d 06h |
/zipcpu/ |
| 183 |
Cleaned up the system so that !CYC implies !STB as well. |
dgisselq |
2772d 06h |
/zipcpu/ |
| 182 |
Bug fix for fast memories. This now works for memories with single cycle
latencies. |
dgisselq |
2772d 06h |
/zipcpu/ |
| 181 |
Adjusted the wishbone logic to include our wishbone simplification that if
CYC is ever low, STB must be low as well. |
dgisselq |
2772d 06h |
/zipcpu/ |
| 180 |
Cleaned up the stall logic--made it independent of whether or not we are
designed to be alternating or not. |
dgisselq |
2772d 06h |
/zipcpu/ |
| 179 |
Lots of changes, most (all?) of them to the non-pipelined core. The resulting
core is now about 100-120 LUTs smaller when not-pipelined, and yet maintains
the pipelined logic when necessary. |
dgisselq |
2772d 06h |
/zipcpu/ |
| 178 |
Rewrote the parameter controlled logic to be just that: perameter controller,
rather than depending upon generics. The result reduces our area by a couple
LUTs. |
dgisselq |
2772d 06h |
/zipcpu/ |
| 177 |
Fixed the illegal address logic to be more precise. |
dgisselq |
2772d 07h |
/zipcpu/ |
| 176 |
Switched from distributed to block RAM, and adjusted the logic to help
timing closure. The resulting core will build in designs up to 200MHz in
speed. |
dgisselq |
2772d 07h |
/zipcpu/ |
