Subversion Repositories zipcpu

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Rev Log message Author Age Path
208 Add install and readme files, updated testb to capture initial variable status in Verilator dgisselq 1756d 09h /zipcpu/
207 Updated the ELF support, and divide test-bench. dgisselq 1756d 09h /zipcpu/
206 Updated assembler, fixes several bugs, adds better bug detection and reporting (fixes some segfaults on bugs) dgisselq 1756d 09h /zipcpu/
205 Updating core to current/best version, to include dblfetch support and full CIS support dgisselq 1756d 09h /zipcpu/
204 Added the two simulators back into the SVN repository dgisselq 1775d 05h /zipcpu/
203 Removed the (now unused) old GCC compiler, v5.3.0 dgisselq 1775d 05h /zipcpu/
202 Additional ZipCPU changes associated w 8b upgrade dgisselq 1775d 06h /zipcpu/
201 RTL files for the 8-bit capable ZipCPU. dgisselq 1775d 07h /zipcpu/
200 Lots of GCC bugs fixed, some new features added, longs should work now. The
build scripts have also been updated and simplified.
dgisselq 1874d 13h /zipcpu/
199 Massive specification rewrite, brings it up to date with the current ZipCPU
state. This does not reflect any major change to the CPU.
dgisselq 1900d 02h /zipcpu/
198 Added a copyright notice. dgisselq 1901d 07h /zipcpu/
197 Added a new multiply testbench. Other changes were necessary to follow. dgisselq 1901d 07h /zipcpu/
196 Updated internal documentation. dgisselq 1901d 07h /zipcpu/
195 Adds a new mode that can handle a delayed stall signal. dgisselq 1901d 07h /zipcpu/
194 Cleaned up some parameters, trying to create more consistency. dgisselq 1901d 07h /zipcpu/
193 These changes make it so the ALU multiplies pass a test-bench. dgisselq 1901d 07h /zipcpu/
192 Fixed a bug with constant alignment in the assembler. dgisselq 1901d 07h /zipcpu/
191 Updated toolchain, more information on the example debugger. dgisselq 1916d 10h /zipcpu/
190 Added the copyright statement back in. dgisselq 1918d 02h /zipcpu/
189 Final, as delivered, ORCONF slides. dgisselq 1918d 02h /zipcpu/

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