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42 Oops -- forgot to add the stack. dgisselq 2554d 20h /zipcpu/
41 Assembly file for the Dhrystone benchmark added. dgisselq 2554d 20h /zipcpu/
40 Quick update, updates the assembly for the new version of the assembler. dgisselq 2554d 20h /zipcpu/
39 Here's the documentation update to support the pipelined read/writes of
the bus from the CPU, as well as the test file that proved they worked.
dgisselq 2557d 23h /zipcpu/
38 A couple of quick updates:

- The Zip CPU now supports pipelined memory access at one clock per
instruction (assuming all the instructions are in the cache)
- There is now a 'zipbones' module to build a Zip System without peripherals.
Any peripherals would then need to be external to the CPU.
- Some bug fixes.

Documentation changes coming shortly.
dgisselq 2558d 01h /zipcpu/
37 Fixed some minor spelling errors. dgisselq 2566d 16h /zipcpu/
36 *Lots* of changes to increase processing speed and remove pipeline stalls.

Removed the useless flash cache, replacing it with a proper DMA controller.

"make test" in the main directory now runs a test program in Verilator and
reports on the results.
dgisselq 2567d 05h /zipcpu/
35 I updated the system diagram to reflect the new version that has a direct
memory access controller, rather than the (useless) manual cache.
dgisselq 2583d 19h /zipcpu/
34 Bunches of changes, although very little changed with the core itself.

Regarding the core, some bugs were fixed within zipcpu.v (the CPU part of the
core), so that the debugger can change the program counter. The debugger
can now halt the CPU and then view, examine, and modify registers to include
the program counter, although live changes to the CC register have not been
tested.

There was also a bug in the stall handling of the wishbone bus delay line. This
has now been fixed.

Moving outwards to the system, some parameters have been added to zipsystem
to make it more configurable for whatever environment you might wish to place
it within. Other minor clean ups have taken place, mostly to the internal
documentation.

Lots of changes, though, to the assembler. The big one is the implementation
of #define macros, C style. Several buggy macros were in sys.i. These have
been fixed. The Makefile has been adjusted so that the build of test.S, which
depends upon sys.i, is now properly dependent upon sys.i for make purposes.
Further, not only will zpp, the assembler preprocessor, handle #define macros,
it will also recursive #defines. The assembler expression evaluator has also
been updated to properly handle both operator precedence, as well as modulo
arithmetic.

The master system test file, test.S, found in the sw/zasm directory has been
updated to reflect these new capabilities. (I really need to move it to the
bench/asm directory, so you may expect that change sometime later.)
dgisselq 2592d 23h /zipcpu/
33 Finally finished a first draft of the full specification! dgisselq 2595d 22h /zipcpu/
32 Updated the document to match the most recent changes to the CPU. Specifically,
these include the re-instatement of the full SUB command with immediate offset,
and ... others I cannot remember.

The new document also describes what conditions create pipeline stalls,
together with how many cycles each stall condition will create.
dgisselq 2596d 06h /zipcpu/
31 README now comments on the relationship between the debugger and the
test bench. (They came from the same code at one time ...)
dgisselq 2596d 07h /zipcpu/
30 Here's a 20% increase in performance: We've gone from 0.44 clocks per
instruction up to 0.53 clocks per instruction on the test.S testset. The
cost? Oh, only about 300 slices.

Not bad.

The specification document will also soon be updated with a list of
conditions that create stalls, as eliminating stalls was how I managed to get
the performance up like I did.
dgisselq 2596d 07h /zipcpu/
29 Not sure what this file was, but it isn't a part of the project anymore. dgisselq 2596d 16h /zipcpu/
28 I got tired of running the make files across multiple directories, so I
built this makefile to coordinate building across each directory.
dgisselq 2596d 16h /zipcpu/
27 The big change to the test bench code in this directory is the support for
non-interactive operation. The test bench will now run in non-interactive
mode until either the CPU HALT's or executes a BUSY instruction. A 'HALT'
is deemed a test success, whereas a BUSY is deemed a test failure.

A usage() statement now informs the user what commands are available while
running the test bench interactively. (It looks a lot like the debugger looks
like, should you manage to get that up and running.)

The make file now also supports interactive and non-interactive testing via
the 'make itest' and 'make test' targets respectively.
dgisselq 2596d 16h /zipcpu/
26 Added signed and unsigned multiply opcodes to the assembler.

An opcode was added for a 'negate' instruction. This is a derived instruction
that turns into two instructions. Neg RX becomes an XOR -1,Rx followed by an
Add 1,Rx command. (Move 1+Rx,Rx would've stalled the bus by one cycle.)

Instructions now keep track of the source linenumber (but not yet filename)
where they were issued. That way, upon an error in linking at the end, the
instruction can be referenced by the proper line number. (Filenames are still
not implemented, hence include files may reference the line number of the
include file with no proper indication of that ... yet).

The OBJFILE intrface now supports a clos() function. This allows the
assembler to close and delete the object file for those cases where the
preprocessor encounters an error.

The master test file, sw/test.S, was adjuted as follows: many of the tests
within it can be separated by #ifdef lines. Hence, if you only wish to test
whether or not CARRY works, undefine all of the other ifdefs but leave the
CARRY_TEST defined. (PUSH_TEST, a test of the PUSH(RX,SP) macro, still doesn't
work because the assembler still doesn't implement macros. This is still a
coming feature.)

The master test file now has tests for the break function, as well as for the
new trap CC bit and the new multiply signed and unsigned instructions in the
ALU.

Many error conditions were added to the assembler preprocessor. Now, if an
EOF is encountered in anything but the INITIAL state (not within a macro),
an error will be created. Likewise, any unrecognized preprocessor directive
will create an error.

The lexical analyzer now supports character values, such as 'a' or '\n' using
a C-type syntax. (Tri-graphs are not supported.) It also supports such
extended syntax as '$GPG'. (Hmm ... wonder why I needed that?)

The lexical analyzer now recognizes and properly supports #line preprocessor
output statements. Theselines are then used to track what source line errors
occurr at.

Operand precedence has been adjusted, so the assembler should be able to
properly handle things like 5+3*8 and get the same number answer as 3*8+5.
(This has been implemented, although not thoroughly tested.)

Upon completion of any preprocessing file, the assembler now checks the status
of the preprocessor as returned by its exit code. Anything other than a zero
status will cause the assembler to delete the resulting object code file it is
building and exit with an error.

The assembler also supports the '-d' command line flag to turn on debugging in
the yacc processor (setting yydebug). It'll produce a lot of debugging output,
but it just might help to figure out what 'syntax error' is actually taking
place.
dgisselq 2596d 17h /zipcpu/
25 Lots of changes, hopefully all for the better. The result works in a
simulator, although it has yet to be tested yet in an FPGA--so it may still
have Xilinx build errors.

1. The wires brought from the CPU to the Zip System for the debug command
register were adjusted. They now include GIE and SLEEP, but no longer include
the step or break enable bits as these were fairly useless anyway.

2. The user and master A-Stall counters were re-labeled as instruction count
counters (which is what they are now anyway). This is for performance reasons
so that, after the fact, you can measure how many instructions per clock
you were actually able to achieve.

3. The CPU debug access port stall was adjusted so that the data port no longer
stalls when the CPU isn't halted. This can be useful, for example, when trying
to determine where th program counter is at without stalling the CPU. (You'll
still need to read two registers, the supervisor and user program counters, and
reading these registers still requires a write to the debug command port first,
so this still requires 4 single operand wishbone bus cycles.)

4. Signed and unsigned 16-bit multiply capabilities were added to the ALU
(cpuops.v) and support added in the Zip CPU master file as well.

5. The ZIP CPU now spports the TRAP bit in the CC register, so that after a user
interrupt the supervisor can tell that it was a user interrupt versus a hardware
interrupt. This bit is set any time the user disables the GIE bit, and cleared
any time the supervisor sets the GIE bit.

6. A reserved position was created in the CC register for a floating point
enable flag. This flag is permanently false, however, on the current
implementation as it doesn't implement floating point.

7. Logic was added to handle the break instruction. This instruction has now
been tested successfully in the simulator. If a break is issued, the CPU will
either halt (if in supervisor mode, or if in user mode with the break enable
bit set in the CC register), or the CPU will trip an interrupt for the
supervisor to transfer execution to a user-level debugging task.

8. After watching the CPU stall on a LDIHI followed by an LDILO, logic was
adjusted to keep the pipeline from stalling in thesee conditions. This lew
logic works for an 'A' operand, or equivalently for a 'B' operand with no
immediate. In the cases of such logic, the operand is loaded directly from the
output of the ALU into the input of the ALU skipping the operand read stage of
the pipelinle. This logic has not been tested on an FPGA yet, so it isn't clear
if it will break timing requirements or not. (Goal is 100 MHz clock.) As
of this new change, the CPU can now execute 0.48 instructions per clock, versus
the 0.44 it was getting before, across the test set.

9. Sleep logic was adjusted to prevent the user from switching to supervisor
mode and putting the processor to (infinite) sleep at the same time. The
justification was the fact that a user should not be able to halt the CPU when
other processes that might want it might still exist.

Other changes were made as well, but to other portions of the project. Those
will be checked in shortly.
dgisselq 2596d 17h /zipcpu/
24 Lots more changes to the spec. It's still not done, but it is more complete
than before.
dgisselq 2599d 07h /zipcpu/
23 Oops -- left some portions of the RTC Clock spec in with the ZIP CPU spec.
These were quickly removed.
dgisselq 2601d 02h /zipcpu/

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