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28 I got tired of running the make files across multiple directories, so I
built this makefile to coordinate building across each directory.
dgisselq 2550d 17h /zipcpu/
27 The big change to the test bench code in this directory is the support for
non-interactive operation. The test bench will now run in non-interactive
mode until either the CPU HALT's or executes a BUSY instruction. A 'HALT'
is deemed a test success, whereas a BUSY is deemed a test failure.

A usage() statement now informs the user what commands are available while
running the test bench interactively. (It looks a lot like the debugger looks
like, should you manage to get that up and running.)

The make file now also supports interactive and non-interactive testing via
the 'make itest' and 'make test' targets respectively.
dgisselq 2550d 17h /zipcpu/
26 Added signed and unsigned multiply opcodes to the assembler.

An opcode was added for a 'negate' instruction. This is a derived instruction
that turns into two instructions. Neg RX becomes an XOR -1,Rx followed by an
Add 1,Rx command. (Move 1+Rx,Rx would've stalled the bus by one cycle.)

Instructions now keep track of the source linenumber (but not yet filename)
where they were issued. That way, upon an error in linking at the end, the
instruction can be referenced by the proper line number. (Filenames are still
not implemented, hence include files may reference the line number of the
include file with no proper indication of that ... yet).

The OBJFILE intrface now supports a clos() function. This allows the
assembler to close and delete the object file for those cases where the
preprocessor encounters an error.

The master test file, sw/test.S, was adjuted as follows: many of the tests
within it can be separated by #ifdef lines. Hence, if you only wish to test
whether or not CARRY works, undefine all of the other ifdefs but leave the
CARRY_TEST defined. (PUSH_TEST, a test of the PUSH(RX,SP) macro, still doesn't
work because the assembler still doesn't implement macros. This is still a
coming feature.)

The master test file now has tests for the break function, as well as for the
new trap CC bit and the new multiply signed and unsigned instructions in the
ALU.

Many error conditions were added to the assembler preprocessor. Now, if an
EOF is encountered in anything but the INITIAL state (not within a macro),
an error will be created. Likewise, any unrecognized preprocessor directive
will create an error.

The lexical analyzer now supports character values, such as 'a' or '\n' using
a C-type syntax. (Tri-graphs are not supported.) It also supports such
extended syntax as '$GPG'. (Hmm ... wonder why I needed that?)

The lexical analyzer now recognizes and properly supports #line preprocessor
output statements. Theselines are then used to track what source line errors
occurr at.

Operand precedence has been adjusted, so the assembler should be able to
properly handle things like 5+3*8 and get the same number answer as 3*8+5.
(This has been implemented, although not thoroughly tested.)

Upon completion of any preprocessing file, the assembler now checks the status
of the preprocessor as returned by its exit code. Anything other than a zero
status will cause the assembler to delete the resulting object code file it is
building and exit with an error.

The assembler also supports the '-d' command line flag to turn on debugging in
the yacc processor (setting yydebug). It'll produce a lot of debugging output,
but it just might help to figure out what 'syntax error' is actually taking
place.
dgisselq 2550d 17h /zipcpu/
25 Lots of changes, hopefully all for the better. The result works in a
simulator, although it has yet to be tested yet in an FPGA--so it may still
have Xilinx build errors.

1. The wires brought from the CPU to the Zip System for the debug command
register were adjusted. They now include GIE and SLEEP, but no longer include
the step or break enable bits as these were fairly useless anyway.

2. The user and master A-Stall counters were re-labeled as instruction count
counters (which is what they are now anyway). This is for performance reasons
so that, after the fact, you can measure how many instructions per clock
you were actually able to achieve.

3. The CPU debug access port stall was adjusted so that the data port no longer
stalls when the CPU isn't halted. This can be useful, for example, when trying
to determine where th program counter is at without stalling the CPU. (You'll
still need to read two registers, the supervisor and user program counters, and
reading these registers still requires a write to the debug command port first,
so this still requires 4 single operand wishbone bus cycles.)

4. Signed and unsigned 16-bit multiply capabilities were added to the ALU
(cpuops.v) and support added in the Zip CPU master file as well.

5. The ZIP CPU now spports the TRAP bit in the CC register, so that after a user
interrupt the supervisor can tell that it was a user interrupt versus a hardware
interrupt. This bit is set any time the user disables the GIE bit, and cleared
any time the supervisor sets the GIE bit.

6. A reserved position was created in the CC register for a floating point
enable flag. This flag is permanently false, however, on the current
implementation as it doesn't implement floating point.

7. Logic was added to handle the break instruction. This instruction has now
been tested successfully in the simulator. If a break is issued, the CPU will
either halt (if in supervisor mode, or if in user mode with the break enable
bit set in the CC register), or the CPU will trip an interrupt for the
supervisor to transfer execution to a user-level debugging task.

8. After watching the CPU stall on a LDIHI followed by an LDILO, logic was
adjusted to keep the pipeline from stalling in thesee conditions. This lew
logic works for an 'A' operand, or equivalently for a 'B' operand with no
immediate. In the cases of such logic, the operand is loaded directly from the
output of the ALU into the input of the ALU skipping the operand read stage of
the pipelinle. This logic has not been tested on an FPGA yet, so it isn't clear
if it will break timing requirements or not. (Goal is 100 MHz clock.) As
of this new change, the CPU can now execute 0.48 instructions per clock, versus
the 0.44 it was getting before, across the test set.

9. Sleep logic was adjusted to prevent the user from switching to supervisor
mode and putting the processor to (infinite) sleep at the same time. The
justification was the fact that a user should not be able to halt the CPU when
other processes that might want it might still exist.

Other changes were made as well, but to other portions of the project. Those
will be checked in shortly.
dgisselq 2550d 18h /zipcpu/
24 Lots more changes to the spec. It's still not done, but it is more complete
than before.
dgisselq 2553d 07h /zipcpu/
23 Oops -- left some portions of the RTC Clock spec in with the ZIP CPU spec.
These were quickly removed.
dgisselq 2555d 03h /zipcpu/
22 dgisselq 2555d 03h /zipcpu/
21 This update adds an incomplete version of the specification for the chip.
I ned to come back to this and do a lot more writing, but it is a start.
dgisselq 2555d 03h /zipcpu/
20 Added a quick README to the debugger directory. dgisselq 2556d 17h /zipcpu/
19 Here's the outlines of a debugger. dgisselq 2556d 17h /zipcpu/

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