URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

[/] [zipcpu/] - Rev 65

Rev	Log message	Author	Age	Path
45	Library routines for 32-bit multiply and divide, both signed and unsigned.	dgisselq	3122d 15h	/zipcpu/
44	??	dgisselq	3122d 15h	/zipcpu/
43	Minor edits to the C++ testbench.	dgisselq	3122d 15h	/zipcpu/
42	Oops -- forgot to add the stack.	dgisselq	3122d 16h	/zipcpu/
41	Assembly file for the Dhrystone benchmark added.	dgisselq	3122d 16h	/zipcpu/
40	Quick update, updates the assembly for the new version of the assembler.	dgisselq	3122d 16h	/zipcpu/
39	Here's the documentation update to support the pipelined read/writes of the bus from the CPU, as well as the test file that proved they worked.	dgisselq	3125d 18h	/zipcpu/
38	A couple of quick updates: - The Zip CPU now supports pipelined memory access at one clock per instruction (assuming all the instructions are in the cache) - There is now a 'zipbones' module to build a Zip System without peripherals. Any peripherals would then need to be external to the CPU. - Some bug fixes. Documentation changes coming shortly.	dgisselq	3125d 20h	/zipcpu/
37	Fixed some minor spelling errors.	dgisselq	3134d 11h	/zipcpu/
36	Lots of changes to increase processing speed and remove pipeline stalls. Removed the useless flash cache, replacing it with a proper DMA controller. "make test" in the main directory now runs a test program in Verilator and reports on the results.	dgisselq	3135d 00h	/zipcpu/