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[/] [zipcpu/] - Rev 72

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72 Some updated graphics, now containing images of the CPU that include the
divide and (currently non-existant) floating point unit.
dgisselq 2598d 09h /zipcpu/
71 This contains a bunch of bug fixes. (A lot ...) For example, the pipeline
stall code has also seriously changed, to fixed the pipeline memory load/op
stage conflict, while maintaining no-stall operation for operands that don't
need an offset. This had a cascading effect, however, so that the multiply
could no longer complete in a single cycle. Therefore, the timing on the
multiplies was slowed down to two cycles from a single cycle. (It's the
only two-cycle ALU operation ...) The illegal instruction code has also been
fixed, so that illegal instructions no longer stalls the prefetch bus.
dgisselq 2598d 10h /zipcpu/
70 Updated the assembler support files, zopcodes in particular, to handle
the disassembly of the new very long instruction word codes.
dgisselq 2598d 10h /zipcpu/
69 This implements the "new Instruction Set" architecture for the Zip CPU. It's
a massive change set, that touches just about everything but probably not
enough of everything. Please see the spec.pdf for a description of this
new architecture.
dgisselq 2604d 14h /zipcpu/
68 Updated specification, includes well illustrated pipeline discussion. dgisselq 2639d 14h /zipcpu/
67 Includes timing diagrams in support of a very descriptive specification section. dgisselq 2639d 14h /zipcpu/
66 Adjusted the support for the DEBUG_SCOPE within these so that it can be
compiled in, or not, based upon an external build configuration file: cpudefs.v.
That allows me to make that file project specific, while the rest of the CPU
is shared among all projects.
dgisselq 2665d 14h /zipcpu/
65 Lots of logic simplifications to the core, in addition to better support for
illegal instruction detection and bus error detection. The biggest change
had to deal with pushing the debug write interface into the ALU write
processing path. This simplifies the logic of adjusting the PC and CC
registers primarily, but also any writes to other registers. It also delays
these register writes by a clock, but since the debug interface is already
ridiculously slow I doubt that matters any.
dgisselq 2665d 14h /zipcpu/
64 Shuffled some comments into here from elsewhere. dgisselq 2665d 14h /zipcpu/
63 Simplified bus interactions, and added support for detecting illegal
instructions (i.e. bus errors) in the pipefetch routine.
dgisselq 2665d 14h /zipcpu/
62 Simplified the subtraction logic, so the carry bit no longer depends on
a separate 32-bit operation but becomes part of the subtract operation.
dgisselq 2665d 14h /zipcpu/
61 Simplified the bus delay logic. Depends upon the stall line being irrelevant
outside of a bus cycle.
dgisselq 2665d 14h /zipcpu/
60 Fixed assembler processing of jump instructions, so that the new fast
return instruction can be used. The test file was modified to test
pipelined value passing within the CPU. That's where the value gets
(re)used before being stored back in the register file. As of this release,
all tests work.
dgisselq 2665d 14h /zipcpu/
59 Adjusted these library routines to use the new stack frame and calling
conventions.
dgisselq 2665d 14h /zipcpu/
58 Added a rudimentary profiling support to the simulator. dgisselq 2665d 15h /zipcpu/
57 Some bug fixes to the dhrystone benchmark, and some compile time defines for
the test bench processor. Of the most important note is the fix to detect
lockups on the debug/wishbone bus--that has been a real help in getting the
ZipCPU installed and the debugger working on the various boards I'm working
with. (i.e., it's helped me find and figure out why/when things haven't worked)
Of other note is the new 'G' key in the testbench code, to cause the test
bench to run without user interaction until the next keystroke. This is
very valuable in long programs, as it makes getting to/from breakpoints
easier (i.e. you don't have to wait as long, hit 'G', breathe, hit 'space'
and you're there).
dgisselq 2675d 17h /zipcpu/
56 Here's a bit of work in progress for getting the Zip CPU working on a XuLA2
board. Many changes include: the existence of a cpudefs.v file to control
what "options" are included in the ZipCPU build. This allows build control
to be separated from the project directory (one build for a XuLA2 board,
another for a Basys-3 development board). Other changes have made things
perhaps harder to read, but they get rid of warnings from XST.

A big change was the addition of the (* ram_style="distributed" *) comment
for the register set. This was necessary to keep XST from inferring a block
RAM and breaking the logic that was supposed to take place between a register
read and when it was used.
dgisselq 2675d 17h /zipcpu/
55 A test was added to double check whether carry following right shifts worked.
This was a necessary part of getting two cycle linear feedback shift register
operations working for a memory test on a XuLA2 board. With this, I can now
verify that such feedback registers work for pseudorandom number purposes.
dgisselq 2675d 17h /zipcpu/
54 This builds on the support for backslash character escapes in both single
and multicharacter expressions. Backslash character escapes are now
possible with quotations and backslashes, and the same code to interpret
the escapes is applied to both single and multicharacter sequences.
dgisselq 2675d 17h /zipcpu/
53 Updated the #include/#define directives to work properly for nested includes.
(They were supposed to work properly for nested includes before ... and didn't)
This fixes those bugs.
dgisselq 2675d 17h /zipcpu/
52 Added the capability to "see" character's encoded within a binary file,
by printing the character value(s) of each opcode (if they are printable)
on each line.
dgisselq 2675d 17h /zipcpu/
51 Added the capability to look at binary files and 'see' characters as they
are encoded in memory.
dgisselq 2675d 17h /zipcpu/
50 Dhrystone benchmark updates--added the copyright notice. (Oops!) dgisselq 2685d 08h /zipcpu/
49 Final set of changes finishing the Dhrystone package. Dhrystone, as
implemented by hand in assembly, now works.
dgisselq 2685d 08h /zipcpu/
48 Files added/updated to get Dhrystone benchmark to work. Several fixes
to the CPU in the process, 'cause it wasn't working. Stall-less ALU
ops now work better, to include grabbing the memory result as it comes out
of the memory unit and placing it straight into either ALU or memory unit
for the next instruction.
dgisselq 2685d 08h /zipcpu/
47 Added some new graphics, includes the file for the Zip Bones system. dgisselq 2685d 08h /zipcpu/
46 A series of updates associated with getting Dhrystone to work. Includes
updates to getting multiple files to link/work together within the assembler,
as well as getting quoted quotations to work in the lexer, and better
include file support in the preprocessor.
dgisselq 2685d 08h /zipcpu/
45 Library routines for 32-bit multiply and divide, both signed and unsigned. dgisselq 2685d 08h /zipcpu/
44 ?? dgisselq 2685d 08h /zipcpu/
43 Minor edits to the C++ testbench. dgisselq 2685d 08h /zipcpu/

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