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Rev Log message Author Age Path
180 Cleaned up the stall logic--made it independent of whether or not we are
designed to be alternating or not.
dgisselq 2110d 03h /zipcpu/trunk/
179 Lots of changes, most (all?) of them to the non-pipelined core. The resulting
core is now about 100-120 LUTs smaller when not-pipelined, and yet maintains
the pipelined logic when necessary.
dgisselq 2110d 03h /zipcpu/trunk/
178 Rewrote the parameter controlled logic to be just that: perameter controller,
rather than depending upon generics. The result reduces our area by a couple
dgisselq 2110d 03h /zipcpu/trunk/
177 Fixed the illegal address logic to be more precise. dgisselq 2110d 03h /zipcpu/trunk/
176 Switched from distributed to block RAM, and adjusted the logic to help
timing closure. The resulting core will build in designs up to 200MHz in
dgisselq 2110d 03h /zipcpu/trunk/
175 Fixed the carry bit for logical shifts: it is the last bit shifted out of the
register. 0x80000000>>32 yields a 0 with carry set. Anything logically
shifted by a number greater than thirty two clears carry and register.
dgisselq 2110d 03h /zipcpu/trunk/
174 Simplified the divide to improve timing performance. dgisselq 2110d 03h /zipcpu/trunk/
173 Adjusted the pdfinfo field, to accommodate Google's bot. dgisselq 2110d 03h /zipcpu/trunk/
172 Added a test to see if the compiler properly handles a large number of
arguments. Further, the sibcall enabled compiler now correcly makes a
sibcall from the end of txreg().
dgisselq 2110d 03h /zipcpu/trunk/
171 This fixes the problem whereby the ZipCPU didn't properly access more than
5 word-sized function parameters.
dgisselq 2112d 08h /zipcpu/trunk/
170 Minor updates to the orconf.pdf pre-conference slide. (Added the 'to be
revealed' line.
dgisselq 2122d 02h /zipcpu/trunk/
169 Added details of LM32 to the (pre) ORConf survey slide in trunk/doc. dgisselq 2158d 03h /zipcpu/trunk/
168 An updated version of the intensive CPU test. This one runs from C, and
requires a UART port and a PIC, but can run quite successfully on multiple
SoCs that have been built with the ZipCPU internal to them.
dgisselq 2171d 02h /zipcpu/trunk/
167 Updated the spec to reflect changes in the CC register: the user break
flag, and the ability to command a clearing of the instruction cache.
dgisselq 2171d 03h /zipcpu/trunk/
166 Bugfix version. This fixes a problem whereby function addresses with offsets
were not properly calculated, together with properly setting up pcrelative
offsets when using the move function together with a label.
dgisselq 2171d 07h /zipcpu/trunk/
165 Added a test to make certain that the arithmetic right shift was properly
propagating the high order bit. (The test works under verilator, but didn't
initially work in Xilinx -- thus a difference between the two.)
dgisselq 2171d 07h /zipcpu/trunk/
164 Updated with inputs from Hellwig Geisse regarding the details of the ECO32
dgisselq 2179d 08h /zipcpu/trunk/
163 Trimmed OR1K instruction set down from 219 instructions, to the minimum number
of 48. Thanks to Olof for helping identify the minimal set!
dgisselq 2187d 10h /zipcpu/trunk/
162 Noted 64-bit integers are by extension, as are vector instructions. dgisselq 2187d 11h /zipcpu/trunk/
161 Initial version of the ORConf slides, showing only the initial CPU survey. dgisselq 2187d 11h /zipcpu/trunk/
160 Logic updates, and bug fix corrections to bring this in line with the current
XuLA2-LX25 SoC version. (i.e., the XuLA version was debugged and improved,
this update pushes those improvements to the mainline.)
dgisselq 2202d 22h /zipcpu/trunk/
159 Now supports building a simulator that can load ELF files, such as GCC and/or
binutils will produce.
dgisselq 2202d 22h /zipcpu/trunk/
158 Now automatically builds the toolchain by default. dgisselq 2202d 23h /zipcpu/trunk/
157 Added the divide unit to the list of ZipCPU dependencies. dgisselq 2202d 23h /zipcpu/trunk/
156 Fixed a compiler warning for an unused result. dgisselq 2202d 23h /zipcpu/trunk/
155 Improved debug trace quality, for finding bugs after the fact. dgisselq 2202d 23h /zipcpu/trunk/
154 Added timing checks on the busy and valid signals: either one of the two is
valid, or the whole is idle.
dgisselq 2202d 23h /zipcpu/trunk/
153 Adds internal link functionality to the specification document format. dgisselq 2202d 23h /zipcpu/trunk/
152 Updated to match the new/updated multiply instructions. Of course, this is
still hand optimized and not compiled--so it's not really a true and proper
test (yet), but ... it's what I have.
dgisselq 2235d 21h /zipcpu/trunk/
151 Minor formatting change. dgisselq 2235d 21h /zipcpu/trunk/

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