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[/] [zipcpu/] [trunk/] - Rev 207

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Rev Log message Author Age Path
207 Updated the ELF support, and divide test-bench. dgisselq 1882d 04h /zipcpu/trunk/
206 Updated assembler, fixes several bugs, adds better bug detection and reporting (fixes some segfaults on bugs) dgisselq 1882d 04h /zipcpu/trunk/
205 Updating core to current/best version, to include dblfetch support and full CIS support dgisselq 1882d 04h /zipcpu/trunk/
204 Added the two simulators back into the SVN repository dgisselq 1900d 23h /zipcpu/trunk/
203 Removed the (now unused) old GCC compiler, v5.3.0 dgisselq 1900d 23h /zipcpu/trunk/
202 Additional ZipCPU changes associated w 8b upgrade dgisselq 1901d 00h /zipcpu/trunk/
201 RTL files for the 8-bit capable ZipCPU. dgisselq 1901d 01h /zipcpu/trunk/
200 Lots of GCC bugs fixed, some new features added, longs should work now. The
build scripts have also been updated and simplified.
dgisselq 2000d 08h /zipcpu/trunk/
199 Massive specification rewrite, brings it up to date with the current ZipCPU
state. This does not reflect any major change to the CPU.
dgisselq 2025d 21h /zipcpu/trunk/
198 Added a copyright notice. dgisselq 2027d 01h /zipcpu/trunk/
197 Added a new multiply testbench. Other changes were necessary to follow. dgisselq 2027d 01h /zipcpu/trunk/
196 Updated internal documentation. dgisselq 2027d 01h /zipcpu/trunk/
195 Adds a new mode that can handle a delayed stall signal. dgisselq 2027d 01h /zipcpu/trunk/
194 Cleaned up some parameters, trying to create more consistency. dgisselq 2027d 01h /zipcpu/trunk/
193 These changes make it so the ALU multiplies pass a test-bench. dgisselq 2027d 01h /zipcpu/trunk/
192 Fixed a bug with constant alignment in the assembler. dgisselq 2027d 01h /zipcpu/trunk/
191 Updated toolchain, more information on the example debugger. dgisselq 2042d 04h /zipcpu/trunk/
190 Added the copyright statement back in. dgisselq 2043d 20h /zipcpu/trunk/
189 Final, as delivered, ORCONF slides. dgisselq 2043d 20h /zipcpu/trunk/
188 Adjusted the opcodes to match the binutils port: added RTN instructions, and
allowed BREAK instructions to include an immediate--to be interpreted by the
debugger.
dgisselq 2075d 23h /zipcpu/trunk/
187 Updated to match changed register definitions within the core. dgisselq 2075d 23h /zipcpu/trunk/
186 Now allows profile dumping for ELF executables. dgisselq 2075d 23h /zipcpu/trunk/
185 Now includes the proper flags for building with ELF executable file support. dgisselq 2075d 23h /zipcpu/trunk/
184 Adjusted the illegal instruction option documentation. dgisselq 2075d 23h /zipcpu/trunk/
183 Cleaned up the system so that !CYC implies !STB as well. dgisselq 2075d 23h /zipcpu/trunk/
182 Bug fix for fast memories. This now works for memories with single cycle
latencies.
dgisselq 2075d 23h /zipcpu/trunk/
181 Adjusted the wishbone logic to include our wishbone simplification that if
CYC is ever low, STB must be low as well.
dgisselq 2075d 23h /zipcpu/trunk/
180 Cleaned up the stall logic--made it independent of whether or not we are
designed to be alternating or not.
dgisselq 2075d 23h /zipcpu/trunk/
179 Lots of changes, most (all?) of them to the non-pipelined core. The resulting
core is now about 100-120 LUTs smaller when not-pipelined, and yet maintains
the pipelined logic when necessary.
dgisselq 2075d 23h /zipcpu/trunk/
178 Rewrote the parameter controlled logic to be just that: perameter controller,
rather than depending upon generics. The result reduces our area by a couple
LUTs.
dgisselq 2075d 23h /zipcpu/trunk/

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