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[/] [zipcpu/] [trunk/] - Rev 83

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83 Added a flag to indicate whether an exception took place on the first
or second half of a VLIW instruction--will be zero in non-VLIW mode,
equivalent to the second half of the instruction having caused the
exception. (Expect these flags to be reordered some time in the future into
a less haphazard ordering ...)

Vastly simplified the pipeline logic, primarily for op_stall, but also touched
opA and opB. (Trying to fit within timing on Spartan 6 ...)

Changed division instruction to include a reset on clear_pipeline, to make
certain [BC $addr; DIV Rx,Ry ] works regardless of whether the condition is
true.
dgisselq 2461d 08h /zipcpu/trunk/
82 Found and (I hope) fixed a nasty bug that would send the prefetch into an
endless loop whenever you jumped to an instruction at the last location
in an unloaded cache line.
dgisselq 2461d 08h /zipcpu/trunk/
81 Trying to clean up ISE generated warnings. dgisselq 2461d 08h /zipcpu/trunk/
80 Bug fix: declared the (combined) multiply to be signed again. Also
changed the name of the generate'd for block, to keep ISE from complaining.
dgisselq 2461d 08h /zipcpu/trunk/
79 Adjusted the opcodes for NOOP, BREAK, and LOCK. dgisselq 2465d 12h /zipcpu/trunk/
78 Found/corrected annoying bug in floating point documentation of the opcode
table.
dgisselq 2465d 12h /zipcpu/trunk/
77 First check-in: the test bench for the divide instruction. dgisselq 2466d 11h /zipcpu/trunk/
76 The biggest change here was to zippy_tb, to make it more similar to the debugger
and to make it work with VLIW-type instructions.
dgisselq 2466d 11h /zipcpu/trunk/
75 Modified for VLIW instructions. dgisselq 2466d 11h /zipcpu/trunk/
74 Added a bunch of debugging code to the Dhrystone benchmark assembly file, as
well as two new testing assembly files.
dgisselq 2466d 11h /zipcpu/trunk/
73 Documentations updates. dgisselq 2466d 11h /zipcpu/trunk/
72 Some updated graphics, now containing images of the CPU that include the
divide and (currently non-existant) floating point unit.
dgisselq 2466d 11h /zipcpu/trunk/
71 This contains a bunch of bug fixes. (A lot ...) For example, the pipeline
stall code has also seriously changed, to fixed the pipeline memory load/op
stage conflict, while maintaining no-stall operation for operands that don't
need an offset. This had a cascading effect, however, so that the multiply
could no longer complete in a single cycle. Therefore, the timing on the
multiplies was slowed down to two cycles from a single cycle. (It's the
only two-cycle ALU operation ...) The illegal instruction code has also been
fixed, so that illegal instructions no longer stalls the prefetch bus.
dgisselq 2466d 11h /zipcpu/trunk/
70 Updated the assembler support files, zopcodes in particular, to handle
the disassembly of the new very long instruction word codes.
dgisselq 2466d 11h /zipcpu/trunk/
69 This implements the "new Instruction Set" architecture for the Zip CPU. It's
a massive change set, that touches just about everything but probably not
enough of everything. Please see the spec.pdf for a description of this
new architecture.
dgisselq 2472d 16h /zipcpu/trunk/
68 Updated specification, includes well illustrated pipeline discussion. dgisselq 2507d 16h /zipcpu/trunk/
67 Includes timing diagrams in support of a very descriptive specification section. dgisselq 2507d 16h /zipcpu/trunk/
66 Adjusted the support for the DEBUG_SCOPE within these so that it can be
compiled in, or not, based upon an external build configuration file: cpudefs.v.
That allows me to make that file project specific, while the rest of the CPU
is shared among all projects.
dgisselq 2533d 16h /zipcpu/trunk/
65 Lots of logic simplifications to the core, in addition to better support for
illegal instruction detection and bus error detection. The biggest change
had to deal with pushing the debug write interface into the ALU write
processing path. This simplifies the logic of adjusting the PC and CC
registers primarily, but also any writes to other registers. It also delays
these register writes by a clock, but since the debug interface is already
ridiculously slow I doubt that matters any.
dgisselq 2533d 16h /zipcpu/trunk/
64 Shuffled some comments into here from elsewhere. dgisselq 2533d 16h /zipcpu/trunk/

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