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[/] [zipcpu/] [trunk/] - Rev 96

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76 The biggest change here was to zippy_tb, to make it more similar to the debugger
and to make it work with VLIW-type instructions.		 dgisselq 3033d 21h /zipcpu/trunk/
75 Modified for VLIW instructions. dgisselq 3033d 21h /zipcpu/trunk/
74 Added a bunch of debugging code to the Dhrystone benchmark assembly file, as
well as two new testing assembly files.		 dgisselq 3033d 21h /zipcpu/trunk/
73 Documentations updates. dgisselq 3033d 21h /zipcpu/trunk/
72 Some updated graphics, now containing images of the CPU that include the
divide and (currently non-existant) floating point unit.		 dgisselq 3033d 21h /zipcpu/trunk/
71 This contains a bunch of bug fixes. (A lot ...) For example, the pipeline
stall code has also seriously changed, to fixed the pipeline memory load/op
stage conflict, while maintaining no-stall operation for operands that don't
need an offset. This had a cascading effect, however, so that the multiply
could no longer complete in a single cycle. Therefore, the timing on the
multiplies was slowed down to two cycles from a single cycle. (It's the
only two-cycle ALU operation ...) The illegal instruction code has also been
fixed, so that illegal instructions no longer stalls the prefetch bus.		 dgisselq 3033d 21h /zipcpu/trunk/
70 Updated the assembler support files, zopcodes in particular, to handle
the disassembly of the new very long instruction word codes.		 dgisselq 3033d 22h /zipcpu/trunk/
69 This implements the "new Instruction Set" architecture for the Zip CPU. It's
a massive change set, that touches just about everything but probably not
enough of everything. Please see the spec.pdf for a description of this
new architecture.		 dgisselq 3040d 02h /zipcpu/trunk/
68 Updated specification, includes well illustrated pipeline discussion. dgisselq 3075d 02h /zipcpu/trunk/
67 Includes timing diagrams in support of a very descriptive specification section. dgisselq 3075d 02h /zipcpu/trunk/

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