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[/] [zipcpu/] [trunk/] [bench/] [asm/] - Rev 172

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172 Added a test to see if the compiler properly handles a large number of
arguments. Further, the sibcall enabled compiler now correcly makes a
sibcall from the end of txreg().
dgisselq 2865d 15h /zipcpu/trunk/bench/asm/
168 An updated version of the intensive CPU test. This one runs from C, and
requires a UART port and a PIC, but can run quite successfully on multiple
SoCs that have been built with the ZipCPU internal to them.
dgisselq 2926d 14h /zipcpu/trunk/bench/asm/
152 Updated to match the new/updated multiply instructions. Of course, this is
still hand optimized and not compiled--so it's not really a true and proper
test (yet), but ... it's what I have.
dgisselq 2991d 09h /zipcpu/trunk/bench/asm/
151 Minor formatting change. dgisselq 2991d 09h /zipcpu/trunk/bench/asm/
150 Minor changes. dgisselq 2991d 09h /zipcpu/trunk/bench/asm/
86 Removed the requirement to have the dev.scope.cpu hardware defined outside
of the Zip CPU (it was defined in another project). This was causing a bus
error in the simulator (which it should have), but taking it out fixes things
in the simulator (while removing capability from one special piece of H/W).
dgisselq 3122d 11h /zipcpu/trunk/bench/asm/
74 Added a bunch of debugging code to the Dhrystone benchmark assembly file, as
well as two new testing assembly files.
dgisselq 3127d 14h /zipcpu/trunk/bench/asm/
69 This implements the "new Instruction Set" architecture for the Zip CPU. It's
a massive change set, that touches just about everything but probably not
enough of everything. Please see the spec.pdf for a description of this
new architecture.
dgisselq 3133d 19h /zipcpu/trunk/bench/asm/
57 Some bug fixes to the dhrystone benchmark, and some compile time defines for
the test bench processor. Of the most important note is the fix to detect
lockups on the debug/wishbone bus--that has been a real help in getting the
ZipCPU installed and the debugger working on the various boards I'm working
with. (i.e., it's helped me find and figure out why/when things haven't worked)
Of other note is the new 'G' key in the testbench code, to cause the test
bench to run without user interaction until the next keystroke. This is
very valuable in long programs, as it makes getting to/from breakpoints
easier (i.e. you don't have to wait as long, hit 'G', breathe, hit 'space'
and you're there).
dgisselq 3204d 21h /zipcpu/trunk/bench/asm/
50 Dhrystone benchmark updates--added the copyright notice. (Oops!) dgisselq 3214d 13h /zipcpu/trunk/bench/asm/
42 Oops -- forgot to add the stack. dgisselq 3214d 13h /zipcpu/trunk/bench/asm/
41 Assembly file for the Dhrystone benchmark added. dgisselq 3214d 13h /zipcpu/trunk/bench/asm/
40 Quick update, updates the assembly for the new version of the assembler. dgisselq 3214d 13h /zipcpu/trunk/bench/asm/
36 *Lots* of changes to increase processing speed and remove pipeline stalls.

Removed the useless flash cache, replacing it with a proper DMA controller.

"make test" in the main directory now runs a test program in Verilator and
reports on the results.
dgisselq 3226d 21h /zipcpu/trunk/bench/asm/
12 Bunch of changes while trying to get a hello world program:
1. Right shifts by 32 or more now result in zero, or all of the top bit in the
case of ASRs.
2. zdump now properly includes addresses with dumped lines.
3. zparser now properly handles immediate values via the .DAT instruction.
dgisselq 3280d 14h /zipcpu/trunk/bench/asm/
11 This version works on an FPGA!!!

(Or at least the wdt.S program passes ...)
dgisselq 3280d 23h /zipcpu/trunk/bench/asm/
10 Here's the watchdog timer code, as well as some pictures of the register
set.
dgisselq 3281d 12h /zipcpu/trunk/bench/asm/
2 An initial load. No promises of what works or not, but this is where the
project is at.
dgisselq 3282d 13h /zipcpu/trunk/bench/asm/

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