Subversion Repositories zipcpu

[/] [zipcpu/] [trunk/] [bench/] [asm/] [wdt.S] - Rev 172


Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
69 This implements the "new Instruction Set" architecture for the Zip CPU. It's
a massive change set, that touches just about everything but probably not
enough of everything. Please see the spec.pdf for a description of this
new architecture.
dgisselq 3136d 20h /zipcpu/trunk/bench/asm/wdt.S
40 Quick update, updates the assembly for the new version of the assembler. dgisselq 3217d 15h /zipcpu/trunk/bench/asm/wdt.S
11 This version works on an FPGA!!!

(Or at least the wdt.S program passes ...)
dgisselq 3284d 01h /zipcpu/trunk/bench/asm/wdt.S
10 Here's the watchdog timer code, as well as some pictures of the register
dgisselq 3284d 14h /zipcpu/trunk/bench/asm/wdt.S

powered by: WebSVN 2.1.0

© copyright 1999-2024, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.