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[/] [zipcpu/] [trunk/] [bench/] [cpp/] [zippy_tb.cpp] - Rev 197

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197 Added a new multiply testbench. Other changes were necessary to follow. dgisselq 2027d 08h /zipcpu/trunk/bench/cpp/zippy_tb.cpp
187 Updated to match changed register definitions within the core. dgisselq 2076d 05h /zipcpu/trunk/bench/cpp/zippy_tb.cpp
155 Improved debug trace quality, for finding bugs after the fact. dgisselq 2169d 02h /zipcpu/trunk/bench/cpp/zippy_tb.cpp
148 Minor changes to get LONG_MPY working, and adjust the documentation. dgisselq 2202d 00h /zipcpu/trunk/bench/cpp/zippy_tb.cpp
140 Minor changes, but fixes build of zippy_tb.cpp. dgisselq 2205d 14h /zipcpu/trunk/bench/cpp/zippy_tb.cpp
134 Working updates, to keep this up to date with the RTL code. dgisselq 2223d 02h /zipcpu/trunk/bench/cpp/zippy_tb.cpp
105 Fixed some nasty early branching bugs. Adjusted the Makefile to declare that
cpudefs.h was automatically generated from cpudefs.v, and made sure that
zipbones included the cpudefs.v so it could get the DEBUG_SCOPE define.
In addition, the test.S was updated to test long jumps, the early branching
bug we found, and all three early branching instructions: ADD #x,PC, LOC(PC),PC,
and LDI #x,PC.
dgisselq 2266d 10h /zipcpu/trunk/bench/cpp/zippy_tb.cpp
87 Adjusted the operator input line to reflect actual logic inputs, rather
than the registered inputs which may have been out of date. (Indeed, they
were out of date for the bug I was chasing and fixed ...)
dgisselq 2333d 02h /zipcpu/trunk/bench/cpp/zippy_tb.cpp
76 The biggest change here was to zippy_tb, to make it more similar to the debugger
and to make it work with VLIW-type instructions.
dgisselq 2338d 05h /zipcpu/trunk/bench/cpp/zippy_tb.cpp
69 This implements the "new Instruction Set" architecture for the Zip CPU. It's
a massive change set, that touches just about everything but probably not
enough of everything. Please see the spec.pdf for a description of this
new architecture.
dgisselq 2344d 10h /zipcpu/trunk/bench/cpp/zippy_tb.cpp
58 Added a rudimentary profiling support to the simulator. dgisselq 2405d 10h /zipcpu/trunk/bench/cpp/zippy_tb.cpp
57 Some bug fixes to the dhrystone benchmark, and some compile time defines for
the test bench processor. Of the most important note is the fix to detect
lockups on the debug/wishbone bus--that has been a real help in getting the
ZipCPU installed and the debugger working on the various boards I'm working
with. (i.e., it's helped me find and figure out why/when things haven't worked)
Of other note is the new 'G' key in the testbench code, to cause the test
bench to run without user interaction until the next keystroke. This is
very valuable in long programs, as it makes getting to/from breakpoints
easier (i.e. you don't have to wait as long, hit 'G', breathe, hit 'space'
and you're there).
dgisselq 2415d 12h /zipcpu/trunk/bench/cpp/zippy_tb.cpp
43 Minor edits to the C++ testbench. dgisselq 2425d 04h /zipcpu/trunk/bench/cpp/zippy_tb.cpp
39 Here's the documentation update to support the pipelined read/writes of
the bus from the CPU, as well as the test file that proved they worked.
dgisselq 2428d 07h /zipcpu/trunk/bench/cpp/zippy_tb.cpp
36 *Lots* of changes to increase processing speed and remove pipeline stalls.

Removed the useless flash cache, replacing it with a proper DMA controller.

"make test" in the main directory now runs a test program in Verilator and
reports on the results.
dgisselq 2437d 13h /zipcpu/trunk/bench/cpp/zippy_tb.cpp
34 Bunches of changes, although very little changed with the core itself.

Regarding the core, some bugs were fixed within zipcpu.v (the CPU part of the
core), so that the debugger can change the program counter. The debugger
can now halt the CPU and then view, examine, and modify registers to include
the program counter, although live changes to the CC register have not been
tested.

There was also a bug in the stall handling of the wishbone bus delay line. This
has now been fixed.

Moving outwards to the system, some parameters have been added to zipsystem
to make it more configurable for whatever environment you might wish to place
it within. Other minor clean ups have taken place, mostly to the internal
documentation.

Lots of changes, though, to the assembler. The big one is the implementation
of #define macros, C style. Several buggy macros were in sys.i. These have
been fixed. The Makefile has been adjusted so that the build of test.S, which
depends upon sys.i, is now properly dependent upon sys.i for make purposes.
Further, not only will zpp, the assembler preprocessor, handle #define macros,
it will also recursive #defines. The assembler expression evaluator has also
been updated to properly handle both operator precedence, as well as modulo
arithmetic.

The master system test file, test.S, found in the sw/zasm directory has been
updated to reflect these new capabilities. (I really need to move it to the
bench/asm directory, so you may expect that change sometime later.)
dgisselq 2463d 07h /zipcpu/trunk/bench/cpp/zippy_tb.cpp
27 The big change to the test bench code in this directory is the support for
non-interactive operation. The test bench will now run in non-interactive
mode until either the CPU HALT's or executes a BUSY instruction. A 'HALT'
is deemed a test success, whereas a BUSY is deemed a test failure.

A usage() statement now informs the user what commands are available while
running the test bench interactively. (It looks a lot like the debugger looks
like, should you manage to get that up and running.)

The make file now also supports interactive and non-interactive testing via
the 'make itest' and 'make test' targets respectively.
dgisselq 2467d 00h /zipcpu/trunk/bench/cpp/zippy_tb.cpp
11 This version works on an FPGA!!!

(Or at least the wdt.S program passes ...)
dgisselq 2491d 14h /zipcpu/trunk/bench/cpp/zippy_tb.cpp
9 This checkin is the result of a watchdog timer test, and everything it took
to get the watchdog timer working. The timer function was simplified,
although it now uses a touch more resources--being able to count down 31
bits instead of 30. The parser was modified, since it couldn't handle
storing to register plus offsets like it was supposed to be able to. The
testbench, zippy_tb, was modified to accept an assembled machine code file
such as I might place on a board to test it.

Lots of work to get it working.

Looking at the files below, it looks like I'll need a second check in to check
in the watchdog timer test itself.
dgisselq 2492d 03h /zipcpu/trunk/bench/cpp/zippy_tb.cpp
8 Fixed the rotate left instruction to work in the zasm parser, and to be
properly referenced in the simulator. The instruction set documentation was
also adjusted to reflect what the CPU actually does.
dgisselq 2492d 10h /zipcpu/trunk/bench/cpp/zippy_tb.cpp

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