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Rev Log message Author Age Path
173 Adjusted the pdfinfo field, to accommodate Google's bot. dgisselq 3220d 13h /zipcpu/trunk/doc/
170 Minor updates to the orconf.pdf pre-conference slide. (Added the 'to be
revealed' line.		 dgisselq 3232d 13h /zipcpu/trunk/doc/
169 Added details of LM32 to the (pre) ORConf survey slide in trunk/doc. dgisselq 3268d 13h /zipcpu/trunk/doc/
167 Updated the spec to reflect changes in the CC register: the user break
flag, and the ability to command a clearing of the instruction cache.		 dgisselq 3281d 13h /zipcpu/trunk/doc/
164 Updated with inputs from Hellwig Geisse regarding the details of the ECO32
CPU.		 dgisselq 3289d 18h /zipcpu/trunk/doc/
163 Trimmed OR1K instruction set down from 219 instructions, to the minimum number
of 48. Thanks to Olof for helping identify the minimal set!		 dgisselq 3297d 20h /zipcpu/trunk/doc/
162 Noted 64-bit integers are by extension, as are vector instructions. dgisselq 3297d 21h /zipcpu/trunk/doc/
161 Initial version of the ORConf slides, showing only the initial CPU survey. dgisselq 3297d 21h /zipcpu/trunk/doc/
153 Adds internal link functionality to the specification document format. dgisselq 3313d 09h /zipcpu/trunk/doc/
139 Changes necessary to document the changed instruction set: LDIHI became MPY,
and MPYU and MPYS became MPYUHI and MPYSHI respectively. See the specification
for more details.		 dgisselq 3352d 18h /zipcpu/trunk/doc/
107 Adding a missing file. dgisselq 3405d 10h /zipcpu/trunk/doc/
106 Updated to allow building without the sources for the graphics used in the
document.		 dgisselq 3405d 14h /zipcpu/trunk/doc/
92 Adjustments made to match the simplified early branching. dgisselq 3451d 11h /zipcpu/trunk/doc/
85 Minor update/correction to operand B definition. dgisselq 3477d 09h /zipcpu/trunk/doc/
79 Adjusted the opcodes for NOOP, BREAK, and LOCK. dgisselq 3481d 13h /zipcpu/trunk/doc/
78 Found/corrected annoying bug in floating point documentation of the opcode
table.		 dgisselq 3481d 13h /zipcpu/trunk/doc/
73 Documentations updates. dgisselq 3482d 12h /zipcpu/trunk/doc/
72 Some updated graphics, now containing images of the CPU that include the
divide and (currently non-existant) floating point unit.		 dgisselq 3482d 12h /zipcpu/trunk/doc/
69 This implements the "new Instruction Set" architecture for the Zip CPU. It's
a massive change set, that touches just about everything but probably not
enough of everything. Please see the spec.pdf for a description of this
new architecture.		 dgisselq 3488d 17h /zipcpu/trunk/doc/
68 Updated specification, includes well illustrated pipeline discussion. dgisselq 3523d 17h /zipcpu/trunk/doc/

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