| Rev |
Log message |
Author |
Age |
Path |
| 202 |
Additional ZipCPU changes associated w 8b upgrade |
dgisselq |
2770d 18h |
/zipcpu/trunk/doc/ |
| 199 |
Massive specification rewrite, brings it up to date with the current ZipCPU
state. This does not reflect any major change to the CPU. |
dgisselq |
2895d 14h |
/zipcpu/trunk/doc/ |
| 190 |
Added the copyright statement back in. |
dgisselq |
2913d 14h |
/zipcpu/trunk/doc/ |
| 189 |
Final, as delivered, ORCONF slides. |
dgisselq |
2913d 14h |
/zipcpu/trunk/doc/ |
| 173 |
Adjusted the pdfinfo field, to accommodate Google's bot. |
dgisselq |
2945d 17h |
/zipcpu/trunk/doc/ |
| 170 |
Minor updates to the orconf.pdf pre-conference slide. (Added the 'to be
revealed' line. |
dgisselq |
2957d 17h |
/zipcpu/trunk/doc/ |
| 169 |
Added details of LM32 to the (pre) ORConf survey slide in trunk/doc. |
dgisselq |
2993d 17h |
/zipcpu/trunk/doc/ |
| 167 |
Updated the spec to reflect changes in the CC register: the user break
flag, and the ability to command a clearing of the instruction cache. |
dgisselq |
3006d 17h |
/zipcpu/trunk/doc/ |
| 164 |
Updated with inputs from Hellwig Geisse regarding the details of the ECO32
CPU. |
dgisselq |
3014d 22h |
/zipcpu/trunk/doc/ |
| 163 |
Trimmed OR1K instruction set down from 219 instructions, to the minimum number
of 48. Thanks to Olof for helping identify the minimal set! |
dgisselq |
3023d 00h |
/zipcpu/trunk/doc/ |
| 162 |
Noted 64-bit integers are by extension, as are vector instructions. |
dgisselq |
3023d 01h |
/zipcpu/trunk/doc/ |
| 161 |
Initial version of the ORConf slides, showing only the initial CPU survey. |
dgisselq |
3023d 01h |
/zipcpu/trunk/doc/ |
| 153 |
Adds internal link functionality to the specification document format. |
dgisselq |
3038d 13h |
/zipcpu/trunk/doc/ |
| 139 |
Changes necessary to document the changed instruction set: LDIHI became MPY,
and MPYU and MPYS became MPYUHI and MPYSHI respectively. See the specification
for more details. |
dgisselq |
3077d 22h |
/zipcpu/trunk/doc/ |
| 107 |
Adding a missing file. |
dgisselq |
3130d 14h |
/zipcpu/trunk/doc/ |
| 106 |
Updated to allow building without the sources for the graphics used in the
document. |
dgisselq |
3130d 18h |
/zipcpu/trunk/doc/ |
| 92 |
Adjustments made to match the simplified early branching. |
dgisselq |
3176d 15h |
/zipcpu/trunk/doc/ |
| 85 |
Minor update/correction to operand B definition. |
dgisselq |
3202d 13h |
/zipcpu/trunk/doc/ |
| 79 |
Adjusted the opcodes for NOOP, BREAK, and LOCK. |
dgisselq |
3206d 17h |
/zipcpu/trunk/doc/ |
| 78 |
Found/corrected annoying bug in floating point documentation of the opcode
table. |
dgisselq |
3206d 17h |
/zipcpu/trunk/doc/ |
| 73 |
Documentations updates. |
dgisselq |
3207d 16h |
/zipcpu/trunk/doc/ |
| 72 |
Some updated graphics, now containing images of the CPU that include the
divide and (currently non-existant) floating point unit. |
dgisselq |
3207d 16h |
/zipcpu/trunk/doc/ |
| 69 |
This implements the "new Instruction Set" architecture for the Zip CPU. It's
a massive change set, that touches just about everything but probably not
enough of everything. Please see the spec.pdf for a description of this
new architecture. |
dgisselq |
3213d 21h |
/zipcpu/trunk/doc/ |
| 68 |
Updated specification, includes well illustrated pipeline discussion. |
dgisselq |
3248d 21h |
/zipcpu/trunk/doc/ |
| 67 |
Includes timing diagrams in support of a very descriptive specification section. |
dgisselq |
3248d 21h |
/zipcpu/trunk/doc/ |
| 49 |
Final set of changes finishing the Dhrystone package. Dhrystone, as
implemented by hand in assembly, now works. |
dgisselq |
3294d 15h |
/zipcpu/trunk/doc/ |
| 47 |
Added some new graphics, includes the file for the Zip Bones system. |
dgisselq |
3294d 15h |
/zipcpu/trunk/doc/ |
| 39 |
Here's the documentation update to support the pipelined read/writes of
the bus from the CPU, as well as the test file that proved they worked. |
dgisselq |
3297d 18h |
/zipcpu/trunk/doc/ |
| 37 |
Fixed some minor spelling errors. |
dgisselq |
3306d 11h |
/zipcpu/trunk/doc/ |
| 36 |
*Lots* of changes to increase processing speed and remove pipeline stalls.
Removed the useless flash cache, replacing it with a proper DMA controller.
"make test" in the main directory now runs a test program in Verilator and
reports on the results. |
dgisselq |
3307d 00h |
/zipcpu/trunk/doc/ |
