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73 Documentations updates. dgisselq 2587d 10h /zipcpu/trunk/doc
72 Some updated graphics, now containing images of the CPU that include the
divide and (currently non-existant) floating point unit.
dgisselq 2587d 10h /zipcpu/trunk/doc
69 This implements the "new Instruction Set" architecture for the Zip CPU. It's
a massive change set, that touches just about everything but probably not
enough of everything. Please see the spec.pdf for a description of this
new architecture.
dgisselq 2593d 14h /zipcpu/trunk/doc
68 Updated specification, includes well illustrated pipeline discussion. dgisselq 2628d 14h /zipcpu/trunk/doc
67 Includes timing diagrams in support of a very descriptive specification section. dgisselq 2628d 15h /zipcpu/trunk/doc
49 Final set of changes finishing the Dhrystone package. Dhrystone, as
implemented by hand in assembly, now works.
dgisselq 2674d 08h /zipcpu/trunk/doc
47 Added some new graphics, includes the file for the Zip Bones system. dgisselq 2674d 08h /zipcpu/trunk/doc
39 Here's the documentation update to support the pipelined read/writes of
the bus from the CPU, as well as the test file that proved they worked.
dgisselq 2677d 11h /zipcpu/trunk/doc
37 Fixed some minor spelling errors. dgisselq 2686d 04h /zipcpu/trunk/doc
36 *Lots* of changes to increase processing speed and remove pipeline stalls.

Removed the useless flash cache, replacing it with a proper DMA controller.

"make test" in the main directory now runs a test program in Verilator and
reports on the results.
dgisselq 2686d 17h /zipcpu/trunk/doc
35 I updated the system diagram to reflect the new version that has a direct
memory access controller, rather than the (useless) manual cache.
dgisselq 2703d 08h /zipcpu/trunk/doc
33 Finally finished a first draft of the full specification! dgisselq 2715d 10h /zipcpu/trunk/doc
32 Updated the document to match the most recent changes to the CPU. Specifically,
these include the re-instatement of the full SUB command with immediate offset,
and ... others I cannot remember.

The new document also describes what conditions create pipeline stalls,
together with how many cycles each stall condition will create.
dgisselq 2715d 18h /zipcpu/trunk/doc
24 Lots more changes to the spec. It's still not done, but it is more complete
than before.
dgisselq 2718d 19h /zipcpu/trunk/doc
23 Oops -- left some portions of the RTC Clock spec in with the ZIP CPU spec.
These were quickly removed.
dgisselq 2720d 15h /zipcpu/trunk/doc
22 dgisselq 2720d 15h /zipcpu/trunk/doc
21 This update adds an incomplete version of the specification for the chip.
I ned to come back to this and do a lot more writing, but it is a start.
dgisselq 2720d 15h /zipcpu/trunk/doc
10 Here's the watchdog timer code, as well as some pictures of the register
set.
dgisselq 2741d 08h /zipcpu/trunk/doc
8 Fixed the rotate left instruction to work in the zasm parser, and to be
properly referenced in the simulator. The instruction set documentation was
also adjusted to reflect what the CPU actually does.
dgisselq 2741d 14h /zipcpu/trunk/doc
7 Here's the iset.html file that was at one time in the gfx directory, but
which could not be moved due to a bad gateway error ... (Grrr).
dgisselq 2741d 15h /zipcpu/trunk/doc

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