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68 Updated specification, includes well illustrated pipeline discussion. dgisselq 2374d 03h /zipcpu/trunk/doc/src/spec.tex
39 Here's the documentation update to support the pipelined read/writes of
the bus from the CPU, as well as the test file that proved they worked.
dgisselq 2423d 00h /zipcpu/trunk/doc/src/spec.tex
37 Fixed some minor spelling errors. dgisselq 2431d 17h /zipcpu/trunk/doc/src/spec.tex
36 *Lots* of changes to increase processing speed and remove pipeline stalls.

Removed the useless flash cache, replacing it with a proper DMA controller.

"make test" in the main directory now runs a test program in Verilator and
reports on the results.
dgisselq 2432d 05h /zipcpu/trunk/doc/src/spec.tex
33 Finally finished a first draft of the full specification! dgisselq 2460d 22h /zipcpu/trunk/doc/src/spec.tex
32 Updated the document to match the most recent changes to the CPU. Specifically,
these include the re-instatement of the full SUB command with immediate offset,
and ... others I cannot remember.

The new document also describes what conditions create pipeline stalls,
together with how many cycles each stall condition will create.
dgisselq 2461d 06h /zipcpu/trunk/doc/src/spec.tex
24 Lots more changes to the spec. It's still not done, but it is more complete
than before.
dgisselq 2464d 07h /zipcpu/trunk/doc/src/spec.tex
23 Oops -- left some portions of the RTC Clock spec in with the ZIP CPU spec.
These were quickly removed.
dgisselq 2466d 03h /zipcpu/trunk/doc/src/spec.tex
22 dgisselq 2466d 03h /zipcpu/trunk/doc/src/spec.tex
21 This update adds an incomplete version of the specification for the chip.
I ned to come back to this and do a lot more writing, but it is a start.
dgisselq 2466d 03h /zipcpu/trunk/doc/src/spec.tex

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