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[/] [zipcpu/] [trunk/] [rtl/] - Rev 199

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Rev Log message Author Age Path
196 Updated internal documentation. dgisselq 2070d 13h /zipcpu/trunk/rtl/
195 Adds a new mode that can handle a delayed stall signal. dgisselq 2070d 13h /zipcpu/trunk/rtl/
194 Cleaned up some parameters, trying to create more consistency. dgisselq 2070d 13h /zipcpu/trunk/rtl/
193 These changes make it so the ALU multiplies pass a test-bench. dgisselq 2070d 13h /zipcpu/trunk/rtl/
184 Adjusted the illegal instruction option documentation. dgisselq 2119d 11h /zipcpu/trunk/rtl/
183 Cleaned up the system so that !CYC implies !STB as well. dgisselq 2119d 11h /zipcpu/trunk/rtl/
182 Bug fix for fast memories. This now works for memories with single cycle
latencies.
dgisselq 2119d 11h /zipcpu/trunk/rtl/
181 Adjusted the wishbone logic to include our wishbone simplification that if
CYC is ever low, STB must be low as well.
dgisselq 2119d 11h /zipcpu/trunk/rtl/
180 Cleaned up the stall logic--made it independent of whether or not we are
designed to be alternating or not.
dgisselq 2119d 11h /zipcpu/trunk/rtl/
179 Lots of changes, most (all?) of them to the non-pipelined core. The resulting
core is now about 100-120 LUTs smaller when not-pipelined, and yet maintains
the pipelined logic when necessary.
dgisselq 2119d 11h /zipcpu/trunk/rtl/
178 Rewrote the parameter controlled logic to be just that: perameter controller,
rather than depending upon generics. The result reduces our area by a couple
LUTs.
dgisselq 2119d 11h /zipcpu/trunk/rtl/
177 Fixed the illegal address logic to be more precise. dgisselq 2119d 11h /zipcpu/trunk/rtl/
176 Switched from distributed to block RAM, and adjusted the logic to help
timing closure. The resulting core will build in designs up to 200MHz in
speed.
dgisselq 2119d 11h /zipcpu/trunk/rtl/
175 Fixed the carry bit for logical shifts: it is the last bit shifted out of the
register. 0x80000000>>32 yields a 0 with carry set. Anything logically
shifted by a number greater than thirty two clears carry and register.
dgisselq 2119d 11h /zipcpu/trunk/rtl/
174 Simplified the divide to improve timing performance. dgisselq 2119d 11h /zipcpu/trunk/rtl/
160 Logic updates, and bug fix corrections to bring this in line with the current
XuLA2-LX25 SoC version. (i.e., the XuLA version was debugged and improved,
this update pushes those improvements to the mainline.)
dgisselq 2212d 07h /zipcpu/trunk/rtl/
157 Added the divide unit to the list of ZipCPU dependencies. dgisselq 2212d 07h /zipcpu/trunk/rtl/
145 This fixes the pipelined memory problem that was introduced a while back to
fix ... pipelined memory conflicts. This appears to maintain the success
of the fix, while recovering the pipeline memory performance that was had
before.
dgisselq 2245d 06h /zipcpu/trunk/rtl/
144 Makes the auto-reload capability a configuration option, and fills out the
reset so that it is properly implemented.
dgisselq 2245d 06h /zipcpu/trunk/rtl/
140 Minor changes, but fixes build of zippy_tb.cpp. dgisselq 2248d 19h /zipcpu/trunk/rtl/

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