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[/] [zipcpu/] [trunk/] [rtl/] [Makefile] - Rev 36

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36 *Lots* of changes to increase processing speed and remove pipeline stalls.

Removed the useless flash cache, replacing it with a proper DMA controller.

"make test" in the main directory now runs a test program in Verilator and
reports on the results.
dgisselq 3225d 12h /zipcpu/trunk/rtl/Makefile
18 A couple of changes: Registers can now be changed via the debug interface.
Also, in anticipation of being able to interrupt the break the processor,
the CPU now exports an interrupt line to the external environment to tell
when it has been halted. Thus, if it gets halted by a break instruction,
the ZipSystem will interrupt whatever's in its environment so that the
debugger can come and examine its state.

Oh, and one other: because you can't examine the state of the CPU without
halting it, I modified the debug control register to export the four
useful flags: break-enable, interrupts enabled, and sleep (step comes for
free in this implementation).
dgisselq 3261d 00h /zipcpu/trunk/rtl/Makefile
2 An initial load. No promises of what works or not, but this is where the
project is at.
dgisselq 3281d 03h /zipcpu/trunk/rtl/Makefile

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