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[/] [zipcpu/] [trunk/] [rtl/] [aux/] - Rev 23

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15 Updated the core CPUOPS module to make certain that the carry was properly
set on right shifts. (Carry is then the last bit shifted out to the right,
and has no relation to the high order bits of the word.) Also fixed a bug
in the busdelay.v file that prevented our Quad SPI flash controller from
working. (This bug fix has not yet been tested ...) Our test.S program, the
closest thing we have to a regression test and found in the sw/zasm directory,
still successfully passes in Verilator.
dgisselq 3151d 02h /zipcpu/trunk/rtl/aux/
2 An initial load. No promises of what works or not, but this is where the
project is at.
dgisselq 3167d 16h /zipcpu/trunk/rtl/aux/

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