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[/] [zipcpu/] [trunk/] [rtl/] [aux/] [wbdblpriarb.v] - Rev 107

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69 This implements the "new Instruction Set" architecture for the Zip CPU. It's
a massive change set, that touches just about everything but probably not
enough of everything. Please see the spec.pdf for a description of this
new architecture.
dgisselq 3211d 09h /zipcpu/trunk/rtl/aux/wbdblpriarb.v
36 *Lots* of changes to increase processing speed and remove pipeline stalls.

Removed the useless flash cache, replacing it with a proper DMA controller.

"make test" in the main directory now runs a test program in Verilator and
reports on the results.
dgisselq 3304d 12h /zipcpu/trunk/rtl/aux/wbdblpriarb.v

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