| Rev |
Log message |
Author |
Age |
Path |
| 63 |
Simplified bus interactions, and added support for detecting illegal
instructions (i.e. bus errors) in the pipefetch routine. |
dgisselq |
3106d 14h |
/zipcpu/trunk/rtl/core/ |
| 62 |
Simplified the subtraction logic, so the carry bit no longer depends on
a separate 32-bit operation but becomes part of the subtract operation. |
dgisselq |
3106d 14h |
/zipcpu/trunk/rtl/core/ |
| 56 |
Here's a bit of work in progress for getting the Zip CPU working on a XuLA2
board. Many changes include: the existence of a cpudefs.v file to control
what "options" are included in the ZipCPU build. This allows build control
to be separated from the project directory (one build for a XuLA2 board,
another for a Basys-3 development board). Other changes have made things
perhaps harder to read, but they get rid of warnings from XST.
A big change was the addition of the (* ram_style="distributed" *) comment
for the register set. This was necessary to keep XST from inferring a block
RAM and breaking the logic that was supposed to take place between a register
read and when it was used. |
dgisselq |
3116d 16h |
/zipcpu/trunk/rtl/core/ |
| 49 |
Final set of changes finishing the Dhrystone package. Dhrystone, as
implemented by hand in assembly, now works. |
dgisselq |
3126d 08h |
/zipcpu/trunk/rtl/core/ |
| 48 |
Files added/updated to get Dhrystone benchmark to work. Several fixes
to the CPU in the process, 'cause it wasn't working. Stall-less ALU
ops now work better, to include grabbing the memory result as it comes out
of the memory unit and placing it straight into either ALU or memory unit
for the next instruction. |
dgisselq |
3126d 08h |
/zipcpu/trunk/rtl/core/ |
| 38 |
A couple of quick updates:
- The Zip CPU now supports pipelined memory access at one clock per
instruction (assuming all the instructions are in the cache)
- There is now a 'zipbones' module to build a Zip System without peripherals.
Any peripherals would then need to be external to the CPU.
- Some bug fixes.
Documentation changes coming shortly. |
dgisselq |
3129d 13h |
/zipcpu/trunk/rtl/core/ |
| 36 |
*Lots* of changes to increase processing speed and remove pipeline stalls.
Removed the useless flash cache, replacing it with a proper DMA controller.
"make test" in the main directory now runs a test program in Verilator and
reports on the results. |
dgisselq |
3138d 17h |
/zipcpu/trunk/rtl/core/ |
| 34 |
Bunches of changes, although very little changed with the core itself.
Regarding the core, some bugs were fixed within zipcpu.v (the CPU part of the
core), so that the debugger can change the program counter. The debugger
can now halt the CPU and then view, examine, and modify registers to include
the program counter, although live changes to the CC register have not been
tested.
There was also a bug in the stall handling of the wishbone bus delay line. This
has now been fixed.
Moving outwards to the system, some parameters have been added to zipsystem
to make it more configurable for whatever environment you might wish to place
it within. Other minor clean ups have taken place, mostly to the internal
documentation.
Lots of changes, though, to the assembler. The big one is the implementation
of #define macros, C style. Several buggy macros were in sys.i. These have
been fixed. The Makefile has been adjusted so that the build of test.S, which
depends upon sys.i, is now properly dependent upon sys.i for make purposes.
Further, not only will zpp, the assembler preprocessor, handle #define macros,
it will also recursive #defines. The assembler expression evaluator has also
been updated to properly handle both operator precedence, as well as modulo
arithmetic.
The master system test file, test.S, found in the sw/zasm directory has been
updated to reflect these new capabilities. (I really need to move it to the
bench/asm directory, so you may expect that change sometime later.) |
dgisselq |
3164d 11h |
/zipcpu/trunk/rtl/core/ |
| 30 |
Here's a 20% increase in performance: We've gone from 0.44 clocks per
instruction up to 0.53 clocks per instruction on the test.S testset. The
cost? Oh, only about 300 slices.
Not bad.
The specification document will also soon be updated with a list of
conditions that create stalls, as eliminating stalls was how I managed to get
the performance up like I did. |
dgisselq |
3167d 19h |
/zipcpu/trunk/rtl/core/ |
| 25 |
Lots of changes, hopefully all for the better. The result works in a
simulator, although it has yet to be tested yet in an FPGA--so it may still
have Xilinx build errors.
1. The wires brought from the CPU to the Zip System for the debug command
register were adjusted. They now include GIE and SLEEP, but no longer include
the step or break enable bits as these were fairly useless anyway.
2. The user and master A-Stall counters were re-labeled as instruction count
counters (which is what they are now anyway). This is for performance reasons
so that, after the fact, you can measure how many instructions per clock
you were actually able to achieve.
3. The CPU debug access port stall was adjusted so that the data port no longer
stalls when the CPU isn't halted. This can be useful, for example, when trying
to determine where th program counter is at without stalling the CPU. (You'll
still need to read two registers, the supervisor and user program counters, and
reading these registers still requires a write to the debug command port first,
so this still requires 4 single operand wishbone bus cycles.)
4. Signed and unsigned 16-bit multiply capabilities were added to the ALU
(cpuops.v) and support added in the Zip CPU master file as well.
5. The ZIP CPU now spports the TRAP bit in the CC register, so that after a user
interrupt the supervisor can tell that it was a user interrupt versus a hardware
interrupt. This bit is set any time the user disables the GIE bit, and cleared
any time the supervisor sets the GIE bit.
6. A reserved position was created in the CC register for a floating point
enable flag. This flag is permanently false, however, on the current
implementation as it doesn't implement floating point.
7. Logic was added to handle the break instruction. This instruction has now
been tested successfully in the simulator. If a break is issued, the CPU will
either halt (if in supervisor mode, or if in user mode with the break enable
bit set in the CC register), or the CPU will trip an interrupt for the
supervisor to transfer execution to a user-level debugging task.
8. After watching the CPU stall on a LDIHI followed by an LDILO, logic was
adjusted to keep the pipeline from stalling in thesee conditions. This lew
logic works for an 'A' operand, or equivalently for a 'B' operand with no
immediate. In the cases of such logic, the operand is loaded directly from the
output of the ALU into the input of the ALU skipping the operand read stage of
the pipelinle. This logic has not been tested on an FPGA yet, so it isn't clear
if it will break timing requirements or not. (Goal is 100 MHz clock.) As
of this new change, the CPU can now execute 0.48 instructions per clock, versus
the 0.44 it was getting before, across the test set.
9. Sleep logic was adjusted to prevent the user from switching to supervisor
mode and putting the processor to (infinite) sleep at the same time. The
justification was the fact that a user should not be able to halt the CPU when
other processes that might want it might still exist.
Other changes were made as well, but to other portions of the project. Those
will be checked in shortly. |
dgisselq |
3168d 05h |
/zipcpu/trunk/rtl/core/ |
