| Rev |
Log message |
Author |
Age |
Path |
| 174 |
Simplified the divide to improve timing performance. |
dgisselq |
2770d 02h |
/zipcpu/trunk/rtl/core/ |
| 160 |
Logic updates, and bug fix corrections to bring this in line with the current
XuLA2-LX25 SoC version. (i.e., the XuLA version was debugged and improved,
this update pushes those improvements to the mainline.) |
dgisselq |
2862d 22h |
/zipcpu/trunk/rtl/core/ |
| 145 |
This fixes the pipelined memory problem that was introduced a while back to
fix ... pipelined memory conflicts. This appears to maintain the success
of the fix, while recovering the pipeline memory performance that was had
before. |
dgisselq |
2895d 21h |
/zipcpu/trunk/rtl/core/ |
| 140 |
Minor changes, but fixes build of zippy_tb.cpp. |
dgisselq |
2899d 10h |
/zipcpu/trunk/rtl/core/ |
| 138 |
This updates the CPU multiply instruction into a set of three instructions.
MPY is a 32x32-bit multiply instruction, returning the low 32-bit result,
MPYUHI returns the upper 32-bits assuming the result was unsigned and MPYSHI
returns the upper 32-bits assuming the result was signed. |
dgisselq |
2902d 08h |
/zipcpu/trunk/rtl/core/ |
| 133 |
Changes preceding an instruction set update, which will change the multiply
operation from a 16x16 bit multiply to three types of 32x32-bit multiplies. |
dgisselq |
2916d 22h |
/zipcpu/trunk/rtl/core/ |
| 132 |
Lots of minor bug fixes. |
dgisselq |
2916d 22h |
/zipcpu/trunk/rtl/core/ |
| 131 |
Fixed a variable use before declaration error. |
dgisselq |
2916d 22h |
/zipcpu/trunk/rtl/core/ |
| 130 |
Simplified the lock logic, and removed it when pipelining was not defined. This
also means the file is now dependent upon cpudefs.v. In another change, brev
was modified so as not to update the flags. This makes it useable with GCC
as a potential move or load immediate instruction. |
dgisselq |
2916d 22h |
/zipcpu/trunk/rtl/core/ |
| 129 |
Bug fix. Fixes some ugly race conditions that would cause code from the wrong
address to be executed. |
dgisselq |
2916d 22h |
/zipcpu/trunk/rtl/core/ |
| 118 |
Fixes two bugs: 1) in the early branching code within the instruction decoder.
This prevented the early branching from working when built with Xilinx's tools,
while the code worked with Verilator. 2) The CPU was not working with the
traditional cache and early branching disabled. These two bugs masked each
other. The replacement code is simpler. |
dgisselq |
2935d 23h |
/zipcpu/trunk/rtl/core/ |
| 105 |
Fixed some nasty early branching bugs. Adjusted the Makefile to declare that
cpudefs.h was automatically generated from cpudefs.v, and made sure that
zipbones included the cpudefs.v so it could get the DEBUG_SCOPE define.
In addition, the test.S was updated to test long jumps, the early branching
bug we found, and all three early branching instructions: ADD #x,PC, LOC(PC),PC,
and LDI #x,PC. |
dgisselq |
2960d 07h |
/zipcpu/trunk/rtl/core/ |
| 91 |
Minor updates. |
dgisselq |
3001d 00h |
/zipcpu/trunk/rtl/core/ |
| 90 |
Removed MOV x(PC),PC from the list of possible early branching instructions.
ADD X,PC and LDI X,PC are now the only recognized early branching instructions.
This was done to spare logic, although I don't think I spared more than a
LUT or two. |
dgisselq |
3001d 00h |
/zipcpu/trunk/rtl/core/ |
| 88 |
Eliminated some warnings. The div fixes were to simplify the logic, even though
the result is less readable ... |
dgisselq |
3025d 00h |
/zipcpu/trunk/rtl/core/ |
| 83 |
Added a flag to indicate whether an exception took place on the first
or second half of a VLIW instruction--will be zero in non-VLIW mode,
equivalent to the second half of the instruction having caused the
exception. (Expect these flags to be reordered some time in the future into
a less haphazard ordering ...)
Vastly simplified the pipeline logic, primarily for op_stall, but also touched
opA and opB. (Trying to fit within timing on Spartan 6 ...)
Changed division instruction to include a reset on clear_pipeline, to make
certain [BC $addr; DIV Rx,Ry ] works regardless of whether the condition is
true. |
dgisselq |
3026d 23h |
/zipcpu/trunk/rtl/core/ |
| 82 |
Found and (I hope) fixed a nasty bug that would send the prefetch into an
endless loop whenever you jumped to an instruction at the last location
in an unloaded cache line. |
dgisselq |
3026d 23h |
/zipcpu/trunk/rtl/core/ |
| 81 |
Trying to clean up ISE generated warnings. |
dgisselq |
3026d 23h |
/zipcpu/trunk/rtl/core/ |
| 80 |
Bug fix: declared the (combined) multiply to be signed again. Also
changed the name of the generate'd for block, to keep ISE from complaining. |
dgisselq |
3026d 23h |
/zipcpu/trunk/rtl/core/ |
| 71 |
This contains a bunch of bug fixes. (A lot ...) For example, the pipeline
stall code has also seriously changed, to fixed the pipeline memory load/op
stage conflict, while maintaining no-stall operation for operands that don't
need an offset. This had a cascading effect, however, so that the multiply
could no longer complete in a single cycle. Therefore, the timing on the
multiplies was slowed down to two cycles from a single cycle. (It's the
only two-cycle ALU operation ...) The illegal instruction code has also been
fixed, so that illegal instructions no longer stalls the prefetch bus. |
dgisselq |
3032d 02h |
/zipcpu/trunk/rtl/core/ |
