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[/] [zipcpu/] [trunk/] [rtl/] [core/] - Rev 175

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Rev	Log message	Author	Age	Path
71	This contains a bunch of bug fixes. (A lot ...) For example, the pipeline stall code has also seriously changed, to fixed the pipeline memory load/op stage conflict, while maintaining no-stall operation for operands that don't need an offset. This had a cascading effect, however, so that the multiply could no longer complete in a single cycle. Therefore, the timing on the multiplies was slowed down to two cycles from a single cycle. (It's the only two-cycle ALU operation ...) The illegal instruction code has also been fixed, so that illegal instructions no longer stalls the prefetch bus.	dgisselq	3039d 17h	/zipcpu/trunk/rtl/core/
69	This implements the "new Instruction Set" architecture for the Zip CPU. It's a massive change set, that touches just about everything but probably not enough of everything. Please see the spec.pdf for a description of this new architecture.	dgisselq	3045d 21h	/zipcpu/trunk/rtl/core/
65	Lots of logic simplifications to the core, in addition to better support for illegal instruction detection and bus error detection. The biggest change had to deal with pushing the debug write interface into the ALU write processing path. This simplifies the logic of adjusting the PC and CC registers primarily, but also any writes to other registers. It also delays these register writes by a clock, but since the debug interface is already ridiculously slow I doubt that matters any.	dgisselq	3106d 21h	/zipcpu/trunk/rtl/core/
63	Simplified bus interactions, and added support for detecting illegal instructions (i.e. bus errors) in the pipefetch routine.	dgisselq	3106d 21h	/zipcpu/trunk/rtl/core/
62	Simplified the subtraction logic, so the carry bit no longer depends on a separate 32-bit operation but becomes part of the subtract operation.	dgisselq	3106d 21h	/zipcpu/trunk/rtl/core/
56	Here's a bit of work in progress for getting the Zip CPU working on a XuLA2 board. Many changes include: the existence of a cpudefs.v file to control what "options" are included in the ZipCPU build. This allows build control to be separated from the project directory (one build for a XuLA2 board, another for a Basys-3 development board). Other changes have made things perhaps harder to read, but they get rid of warnings from XST. A big change was the addition of the (* ram_style="distributed" *) comment for the register set. This was necessary to keep XST from inferring a block RAM and breaking the logic that was supposed to take place between a register read and when it was used.	dgisselq	3117d 00h	/zipcpu/trunk/rtl/core/
49	Final set of changes finishing the Dhrystone package. Dhrystone, as implemented by hand in assembly, now works.	dgisselq	3126d 15h	/zipcpu/trunk/rtl/core/
48	Files added/updated to get Dhrystone benchmark to work. Several fixes to the CPU in the process, 'cause it wasn't working. Stall-less ALU ops now work better, to include grabbing the memory result as it comes out of the memory unit and placing it straight into either ALU or memory unit for the next instruction.	dgisselq	3126d 15h	/zipcpu/trunk/rtl/core/
38	A couple of quick updates: - The Zip CPU now supports pipelined memory access at one clock per instruction (assuming all the instructions are in the cache) - There is now a 'zipbones' module to build a Zip System without peripherals. Any peripherals would then need to be external to the CPU. - Some bug fixes. Documentation changes coming shortly.	dgisselq	3129d 21h	/zipcpu/trunk/rtl/core/
36	Lots of changes to increase processing speed and remove pipeline stalls. Removed the useless flash cache, replacing it with a proper DMA controller. "make test" in the main directory now runs a test program in Verilator and reports on the results.	dgisselq	3139d 00h	/zipcpu/trunk/rtl/core/

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