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[/] [zipcpu/] [trunk/] [rtl/] [core/] [cpuops.v] - Rev 3

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3 Rebuilt the pipefetch (instruction fetch/cache module) so that it will
let go of the bus if the memory unit wants it to execute an instruction.
Pipefetch will then grab the bus back whtn the memory unit is done, so things
otherwise continue as they were before.

Other tweaks were made to try to reduce code complexity.
dgisselq 2485d 09h /zipcpu/trunk/rtl/core/cpuops.v
2 An initial load. No promises of what works or not, but this is where the
project is at.
dgisselq 2486d 02h /zipcpu/trunk/rtl/core/cpuops.v

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