URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

[/] [zipcpu/] [trunk/] [rtl/] [core/] [div.v] - Rev 209

Rev	Log message	Author	Age	Path
209	8b bytes, + formal verification throughout + dcache	dgisselq	1856d 23h	/zipcpu/trunk/rtl/core/div.v
205	Updating core to current/best version, to include dblfetch support and full CIS support	dgisselq	2577d 11h	/zipcpu/trunk/rtl/core/div.v
201	RTL files for the 8-bit capable ZipCPU.	dgisselq	2596d 08h	/zipcpu/trunk/rtl/core/div.v
196	Updated internal documentation.	dgisselq	2722d 08h	/zipcpu/trunk/rtl/core/div.v
174	Simplified the divide to improve timing performance.	dgisselq	2771d 06h	/zipcpu/trunk/rtl/core/div.v
160	Logic updates, and bug fix corrections to bring this in line with the current XuLA2-LX25 SoC version. (i.e., the XuLA version was debugged and improved, this update pushes those improvements to the mainline.)	dgisselq	2864d 02h	/zipcpu/trunk/rtl/core/div.v
88	Eliminated some warnings. The div fixes were to simplify the logic, even though the result is less readable ...	dgisselq	3026d 04h	/zipcpu/trunk/rtl/core/div.v
81	Trying to clean up ISE generated warnings.	dgisselq	3028d 03h	/zipcpu/trunk/rtl/core/div.v
69	This implements the "new Instruction Set" architecture for the Zip CPU. It's a massive change set, that touches just about everything but probably not enough of everything. Please see the spec.pdf for a description of this new architecture.	dgisselq	3039d 10h	/zipcpu/trunk/rtl/core/div.v