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[/] [zipcpu/] [trunk/] [rtl/] [core/] [memops.v] - Rev 65

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48 Files added/updated to get Dhrystone benchmark to work. Several fixes
to the CPU in the process, 'cause it wasn't working. Stall-less ALU
ops now work better, to include grabbing the memory result as it comes out
of the memory unit and placing it straight into either ALU or memory unit
for the next instruction.
dgisselq 2510d 09h /zipcpu/trunk/rtl/core/memops.v
36 *Lots* of changes to increase processing speed and remove pipeline stalls.

Removed the useless flash cache, replacing it with a proper DMA controller.

"make test" in the main directory now runs a test program in Verilator and
reports on the results.
dgisselq 2522d 17h /zipcpu/trunk/rtl/core/memops.v
3 Rebuilt the pipefetch (instruction fetch/cache module) so that it will
let go of the bus if the memory unit wants it to execute an instruction.
Pipefetch will then grab the bus back whtn the memory unit is done, so things
otherwise continue as they were before.

Other tweaks were made to try to reduce code complexity.
dgisselq 2577d 16h /zipcpu/trunk/rtl/core/memops.v
2 An initial load. No promises of what works or not, but this is where the
project is at.
dgisselq 2578d 09h /zipcpu/trunk/rtl/core/memops.v

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