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[/] [zipcpu/] [trunk/] [rtl/] [core/] [pipefetch.v] - Rev 209


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209 8b bytes, + formal verification throughout + dcache dgisselq 989d 00h /zipcpu/trunk/rtl/core/pipefetch.v
201 RTL files for the 8-bit capable ZipCPU. dgisselq 1728d 09h /zipcpu/trunk/rtl/core/pipefetch.v
177 Fixed the illegal address logic to be more precise. dgisselq 1903d 07h /zipcpu/trunk/rtl/core/pipefetch.v
69 This implements the "new Instruction Set" architecture for the Zip CPU. It's
a massive change set, that touches just about everything but probably not
enough of everything. Please see the spec.pdf for a description of this
new architecture.
dgisselq 2171d 11h /zipcpu/trunk/rtl/core/pipefetch.v
63 Simplified bus interactions, and added support for detecting illegal
instructions (i.e. bus errors) in the pipefetch routine.
dgisselq 2232d 11h /zipcpu/trunk/rtl/core/pipefetch.v
56 Here's a bit of work in progress for getting the Zip CPU working on a XuLA2
board. Many changes include: the existence of a cpudefs.v file to control
what "options" are included in the ZipCPU build. This allows build control
to be separated from the project directory (one build for a XuLA2 board,
another for a Basys-3 development board). Other changes have made things
perhaps harder to read, but they get rid of warnings from XST.

A big change was the addition of the (* ram_style="distributed" *) comment
for the register set. This was necessary to keep XST from inferring a block
RAM and breaking the logic that was supposed to take place between a register
read and when it was used.
dgisselq 2242d 14h /zipcpu/trunk/rtl/core/pipefetch.v
48 Files added/updated to get Dhrystone benchmark to work. Several fixes
to the CPU in the process, 'cause it wasn't working. Stall-less ALU
ops now work better, to include grabbing the memory result as it comes out
of the memory unit and placing it straight into either ALU or memory unit
for the next instruction.
dgisselq 2252d 05h /zipcpu/trunk/rtl/core/pipefetch.v
38 A couple of quick updates:

- The Zip CPU now supports pipelined memory access at one clock per
instruction (assuming all the instructions are in the cache)
- There is now a 'zipbones' module to build a Zip System without peripherals.
Any peripherals would then need to be external to the CPU.
- Some bug fixes.

Documentation changes coming shortly.
dgisselq 2255d 11h /zipcpu/trunk/rtl/core/pipefetch.v
36 *Lots* of changes to increase processing speed and remove pipeline stalls.

Removed the useless flash cache, replacing it with a proper DMA controller.

"make test" in the main directory now runs a test program in Verilator and
reports on the results.
dgisselq 2264d 14h /zipcpu/trunk/rtl/core/pipefetch.v
18 A couple of changes: Registers can now be changed via the debug interface.
Also, in anticipation of being able to interrupt the break the processor,
the CPU now exports an interrupt line to the external environment to tell
when it has been halted. Thus, if it gets halted by a break instruction,
the ZipSystem will interrupt whatever's in its environment so that the
debugger can come and examine its state.

Oh, and one other: because you can't examine the state of the CPU without
halting it, I modified the debug control register to export the four
useful flags: break-enable, interrupts enabled, and sleep (step comes for
free in this implementation).
dgisselq 2300d 02h /zipcpu/trunk/rtl/core/pipefetch.v
11 This version works on an FPGA!!!

(Or at least the wdt.S program passes ...)
dgisselq 2318d 15h /zipcpu/trunk/rtl/core/pipefetch.v
3 Rebuilt the pipefetch (instruction fetch/cache module) so that it will
let go of the bus if the memory unit wants it to execute an instruction.
Pipefetch will then grab the bus back whtn the memory unit is done, so things
otherwise continue as they were before.

Other tweaks were made to try to reduce code complexity.
dgisselq 2319d 12h /zipcpu/trunk/rtl/core/pipefetch.v
2 An initial load. No promises of what works or not, but this is where the
project is at.
dgisselq 2320d 06h /zipcpu/trunk/rtl/core/pipefetch.v

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