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[/] [zipcpu/] [trunk/] [rtl/] [core/] [pipefetch.v] - Rev 48

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48 Files added/updated to get Dhrystone benchmark to work. Several fixes
to the CPU in the process, 'cause it wasn't working. Stall-less ALU
ops now work better, to include grabbing the memory result as it comes out
of the memory unit and placing it straight into either ALU or memory unit
for the next instruction.		 dgisselq 3121d 04h /zipcpu/trunk/rtl/core/pipefetch.v
38 A couple of quick updates:

- The Zip CPU now supports pipelined memory access at one clock per
instruction (assuming all the instructions are in the cache)
- There is now a 'zipbones' module to build a Zip System without peripherals.
Any peripherals would then need to be external to the CPU.
- Some bug fixes.

Documentation changes coming shortly.		 dgisselq 3124d 09h /zipcpu/trunk/rtl/core/pipefetch.v
36 *Lots* of changes to increase processing speed and remove pipeline stalls.

Removed the useless flash cache, replacing it with a proper DMA controller.

"make test" in the main directory now runs a test program in Verilator and
reports on the results.		 dgisselq 3133d 13h /zipcpu/trunk/rtl/core/pipefetch.v
18 A couple of changes: Registers can now be changed via the debug interface.
Also, in anticipation of being able to interrupt the break the processor,
the CPU now exports an interrupt line to the external environment to tell
when it has been halted. Thus, if it gets halted by a break instruction,
the ZipSystem will interrupt whatever's in its environment so that the
debugger can come and examine its state.

Oh, and one other: because you can't examine the state of the CPU without
halting it, I modified the debug control register to export the four
useful flags: break-enable, interrupts enabled, and sleep (step comes for
free in this implementation).		 dgisselq 3169d 01h /zipcpu/trunk/rtl/core/pipefetch.v
11 This version works on an FPGA!!!

(Or at least the wdt.S program passes ...)		 dgisselq 3187d 14h /zipcpu/trunk/rtl/core/pipefetch.v
3 Rebuilt the pipefetch (instruction fetch/cache module) so that it will
let go of the bus if the memory unit wants it to execute an instruction.
Pipefetch will then grab the bus back whtn the memory unit is done, so things
otherwise continue as they were before.

Other tweaks were made to try to reduce code complexity.		 dgisselq 3188d 11h /zipcpu/trunk/rtl/core/pipefetch.v
2 An initial load. No promises of what works or not, but this is where the
project is at.		 dgisselq 3189d 04h /zipcpu/trunk/rtl/core/pipefetch.v

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