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[/] [zipcpu/] [trunk/] [rtl/] [core] - Rev 209

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Rev	Log message	Author	Age	Path
209	8b bytes, + formal verification throughout + dcache	dgisselq	1859d 05h	/zipcpu/trunk/rtl/core
205	Updating core to current/best version, to include dblfetch support and full CIS support	dgisselq	2579d 17h	/zipcpu/trunk/rtl/core
201	RTL files for the 8-bit capable ZipCPU.	dgisselq	2598d 15h	/zipcpu/trunk/rtl/core
196	Updated internal documentation.	dgisselq	2724d 14h	/zipcpu/trunk/rtl/core
194	Cleaned up some parameters, trying to create more consistency.	dgisselq	2724d 14h	/zipcpu/trunk/rtl/core
193	These changes make it so the ALU multiplies pass a test-bench.	dgisselq	2724d 14h	/zipcpu/trunk/rtl/core
179	Lots of changes, most (all?) of them to the non-pipelined core. The resulting core is now about 100-120 LUTs smaller when not-pipelined, and yet maintains the pipelined logic when necessary.	dgisselq	2773d 12h	/zipcpu/trunk/rtl/core
178	Rewrote the parameter controlled logic to be just that: perameter controller, rather than depending upon generics. The result reduces our area by a couple LUTs.	dgisselq	2773d 12h	/zipcpu/trunk/rtl/core
177	Fixed the illegal address logic to be more precise.	dgisselq	2773d 13h	/zipcpu/trunk/rtl/core
176	Switched from distributed to block RAM, and adjusted the logic to help timing closure. The resulting core will build in designs up to 200MHz in speed.	dgisselq	2773d 13h	/zipcpu/trunk/rtl/core
175	Fixed the carry bit for logical shifts: it is the last bit shifted out of the register. 0x80000000>>32 yields a 0 with carry set. Anything logically shifted by a number greater than thirty two clears carry and register.	dgisselq	2773d 13h	/zipcpu/trunk/rtl/core
174	Simplified the divide to improve timing performance.	dgisselq	2773d 13h	/zipcpu/trunk/rtl/core
160	Logic updates, and bug fix corrections to bring this in line with the current XuLA2-LX25 SoC version. (i.e., the XuLA version was debugged and improved, this update pushes those improvements to the mainline.)	dgisselq	2866d 08h	/zipcpu/trunk/rtl/core
145	This fixes the pipelined memory problem that was introduced a while back to fix ... pipelined memory conflicts. This appears to maintain the success of the fix, while recovering the pipeline memory performance that was had before.	dgisselq	2899d 07h	/zipcpu/trunk/rtl/core
140	Minor changes, but fixes build of zippy_tb.cpp.	dgisselq	2902d 20h	/zipcpu/trunk/rtl/core
138	This updates the CPU multiply instruction into a set of three instructions. MPY is a 32x32-bit multiply instruction, returning the low 32-bit result, MPYUHI returns the upper 32-bits assuming the result was unsigned and MPYSHI returns the upper 32-bits assuming the result was signed.	dgisselq	2905d 18h	/zipcpu/trunk/rtl/core
133	Changes preceding an instruction set update, which will change the multiply operation from a 16x16 bit multiply to three types of 32x32-bit multiplies.	dgisselq	2920d 08h	/zipcpu/trunk/rtl/core
132	Lots of minor bug fixes.	dgisselq	2920d 08h	/zipcpu/trunk/rtl/core
131	Fixed a variable use before declaration error.	dgisselq	2920d 09h	/zipcpu/trunk/rtl/core
130	Simplified the lock logic, and removed it when pipelining was not defined. This also means the file is now dependent upon cpudefs.v. In another change, brev was modified so as not to update the flags. This makes it useable with GCC as a potential move or load immediate instruction.	dgisselq	2920d 09h	/zipcpu/trunk/rtl/core

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[/] [zipcpu/] [trunk/] [rtl/] [core] - Rev 209

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