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196 Updated internal documentation. dgisselq 2028d 04h /zipcpu/trunk/rtl/core
194 Cleaned up some parameters, trying to create more consistency. dgisselq 2028d 04h /zipcpu/trunk/rtl/core
193 These changes make it so the ALU multiplies pass a test-bench. dgisselq 2028d 04h /zipcpu/trunk/rtl/core
179 Lots of changes, most (all?) of them to the non-pipelined core. The resulting
core is now about 100-120 LUTs smaller when not-pipelined, and yet maintains
the pipelined logic when necessary.
dgisselq 2077d 02h /zipcpu/trunk/rtl/core
178 Rewrote the parameter controlled logic to be just that: perameter controller,
rather than depending upon generics. The result reduces our area by a couple
dgisselq 2077d 02h /zipcpu/trunk/rtl/core
177 Fixed the illegal address logic to be more precise. dgisselq 2077d 02h /zipcpu/trunk/rtl/core
176 Switched from distributed to block RAM, and adjusted the logic to help
timing closure. The resulting core will build in designs up to 200MHz in
dgisselq 2077d 02h /zipcpu/trunk/rtl/core
175 Fixed the carry bit for logical shifts: it is the last bit shifted out of the
register. 0x80000000>>32 yields a 0 with carry set. Anything logically
shifted by a number greater than thirty two clears carry and register.
dgisselq 2077d 02h /zipcpu/trunk/rtl/core
174 Simplified the divide to improve timing performance. dgisselq 2077d 02h /zipcpu/trunk/rtl/core
160 Logic updates, and bug fix corrections to bring this in line with the current
XuLA2-LX25 SoC version. (i.e., the XuLA version was debugged and improved,
this update pushes those improvements to the mainline.)
dgisselq 2169d 22h /zipcpu/trunk/rtl/core
145 This fixes the pipelined memory problem that was introduced a while back to
fix ... pipelined memory conflicts. This appears to maintain the success
of the fix, while recovering the pipeline memory performance that was had
dgisselq 2202d 20h /zipcpu/trunk/rtl/core
140 Minor changes, but fixes build of zippy_tb.cpp. dgisselq 2206d 10h /zipcpu/trunk/rtl/core
138 This updates the CPU multiply instruction into a set of three instructions.
MPY is a 32x32-bit multiply instruction, returning the low 32-bit result,
MPYUHI returns the upper 32-bits assuming the result was unsigned and MPYSHI
returns the upper 32-bits assuming the result was signed.
dgisselq 2209d 07h /zipcpu/trunk/rtl/core
133 Changes preceding an instruction set update, which will change the multiply
operation from a 16x16 bit multiply to three types of 32x32-bit multiplies.
dgisselq 2223d 22h /zipcpu/trunk/rtl/core
132 Lots of minor bug fixes. dgisselq 2223d 22h /zipcpu/trunk/rtl/core
131 Fixed a variable use before declaration error. dgisselq 2223d 22h /zipcpu/trunk/rtl/core
130 Simplified the lock logic, and removed it when pipelining was not defined. This
also means the file is now dependent upon cpudefs.v. In another change, brev
was modified so as not to update the flags. This makes it useable with GCC
as a potential move or load immediate instruction.
dgisselq 2223d 22h /zipcpu/trunk/rtl/core
129 Bug fix. Fixes some ugly race conditions that would cause code from the wrong
address to be executed.
dgisselq 2223d 22h /zipcpu/trunk/rtl/core
118 Fixes two bugs: 1) in the early branching code within the instruction decoder.
This prevented the early branching from working when built with Xilinx's tools,
while the code worked with Verilator. 2) The CPU was not working with the
traditional cache and early branching disabled. These two bugs masked each
other. The replacement code is simpler.
dgisselq 2242d 23h /zipcpu/trunk/rtl/core
105 Fixed some nasty early branching bugs. Adjusted the Makefile to declare that
cpudefs.h was automatically generated from cpudefs.v, and made sure that
zipbones included the cpudefs.v so it could get the DEBUG_SCOPE define.
In addition, the test.S was updated to test long jumps, the early branching
bug we found, and all three early branching instructions: ADD #x,PC, LOC(PC),PC,
and LDI #x,PC.
dgisselq 2267d 07h /zipcpu/trunk/rtl/core

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