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[/] [zipcpu/] [trunk/] [rtl/] [core] - Rev 209

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129 Bug fix. Fixes some ugly race conditions that would cause code from the wrong
address to be executed.		 dgisselq 2925d 08h /zipcpu/trunk/rtl/core
118 Fixes two bugs: 1) in the early branching code within the instruction decoder.
This prevented the early branching from working when built with Xilinx's tools,
while the code worked with Verilator. 2) The CPU was not working with the
traditional cache and early branching disabled. These two bugs masked each
other. The replacement code is simpler.		 dgisselq 2944d 09h /zipcpu/trunk/rtl/core
105 Fixed some nasty early branching bugs. Adjusted the Makefile to declare that
cpudefs.h was automatically generated from cpudefs.v, and made sure that
zipbones included the cpudefs.v so it could get the DEBUG_SCOPE define.
In addition, the test.S was updated to test long jumps, the early branching
bug we found, and all three early branching instructions: ADD #x,PC, LOC(PC),PC,
and LDI #x,PC.		 dgisselq 2968d 17h /zipcpu/trunk/rtl/core
91 Minor updates. dgisselq 3009d 10h /zipcpu/trunk/rtl/core
90 Removed MOV x(PC),PC from the list of possible early branching instructions.
ADD X,PC and LDI X,PC are now the only recognized early branching instructions.
This was done to spare logic, although I don't think I spared more than a
LUT or two.		 dgisselq 3009d 10h /zipcpu/trunk/rtl/core
88 Eliminated some warnings. The div fixes were to simplify the logic, even though
the result is less readable ...		 dgisselq 3033d 10h /zipcpu/trunk/rtl/core
83 Added a flag to indicate whether an exception took place on the first
or second half of a VLIW instruction--will be zero in non-VLIW mode,
equivalent to the second half of the instruction having caused the
exception. (Expect these flags to be reordered some time in the future into
a less haphazard ordering ...)

Vastly simplified the pipeline logic, primarily for op_stall, but also touched
opA and opB. (Trying to fit within timing on Spartan 6 ...)

Changed division instruction to include a reset on clear_pipeline, to make
certain [BC $addr; DIV Rx,Ry ] works regardless of whether the condition is
true.		 dgisselq 3035d 09h /zipcpu/trunk/rtl/core
82 Found and (I hope) fixed a nasty bug that would send the prefetch into an
endless loop whenever you jumped to an instruction at the last location
in an unloaded cache line.		 dgisselq 3035d 09h /zipcpu/trunk/rtl/core
81 Trying to clean up ISE generated warnings. dgisselq 3035d 09h /zipcpu/trunk/rtl/core
80 Bug fix: declared the (combined) multiply to be signed again. Also
changed the name of the generate'd for block, to keep ISE from complaining.		 dgisselq 3035d 09h /zipcpu/trunk/rtl/core

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