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[/] [zipcpu/] [trunk/] [rtl/] [cpudefs.v] - Rev 209

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209 8b bytes, + formal verification throughout + dcache dgisselq 984d 01h /zipcpu/trunk/rtl/cpudefs.v
205 Updating core to current/best version, to include dblfetch support and full CIS support dgisselq 1704d 13h /zipcpu/trunk/rtl/cpudefs.v
201 RTL files for the 8-bit capable ZipCPU. dgisselq 1723d 10h /zipcpu/trunk/rtl/cpudefs.v
193 These changes make it so the ALU multiplies pass a test-bench. dgisselq 1849d 10h /zipcpu/trunk/rtl/cpudefs.v
184 Adjusted the illegal instruction option documentation. dgisselq 1898d 08h /zipcpu/trunk/rtl/cpudefs.v
138 This updates the CPU multiply instruction into a set of three instructions.
MPY is a 32x32-bit multiply instruction, returning the low 32-bit result,
MPYUHI returns the upper 32-bits assuming the result was unsigned and MPYSHI
returns the upper 32-bits assuming the result was signed.
dgisselq 2030d 14h /zipcpu/trunk/rtl/cpudefs.v
84 Minor updates. dgisselq 2155d 05h /zipcpu/trunk/rtl/cpudefs.v
71 This contains a bunch of bug fixes. (A lot ...) For example, the pipeline
stall code has also seriously changed, to fixed the pipeline memory load/op
stage conflict, while maintaining no-stall operation for operands that don't
need an offset. This had a cascading effect, however, so that the multiply
could no longer complete in a single cycle. Therefore, the timing on the
multiplies was slowed down to two cycles from a single cycle. (It's the
only two-cycle ALU operation ...) The illegal instruction code has also been
fixed, so that illegal instructions no longer stalls the prefetch bus.
dgisselq 2160d 08h /zipcpu/trunk/rtl/cpudefs.v
69 This implements the "new Instruction Set" architecture for the Zip CPU. It's
a massive change set, that touches just about everything but probably not
enough of everything. Please see the spec.pdf for a description of this
new architecture.
dgisselq 2166d 12h /zipcpu/trunk/rtl/cpudefs.v
64 Shuffled some comments into here from elsewhere. dgisselq 2227d 13h /zipcpu/trunk/rtl/cpudefs.v
56 Here's a bit of work in progress for getting the Zip CPU working on a XuLA2
board. Many changes include: the existence of a cpudefs.v file to control
what "options" are included in the ZipCPU build. This allows build control
to be separated from the project directory (one build for a XuLA2 board,
another for a Basys-3 development board). Other changes have made things
perhaps harder to read, but they get rid of warnings from XST.

A big change was the addition of the (* ram_style="distributed" *) comment
for the register set. This was necessary to keep XST from inferring a block
RAM and breaking the logic that was supposed to take place between a register
read and when it was used.
dgisselq 2237d 15h /zipcpu/trunk/rtl/cpudefs.v

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