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[/] [zipcpu/] [trunk/] [rtl/] [peripherals/] - Rev 36

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36 *Lots* of changes to increase processing speed and remove pipeline stalls.

Removed the useless flash cache, replacing it with a proper DMA controller.

"make test" in the main directory now runs a test program in Verilator and
reports on the results.
dgisselq 2477d 11h /zipcpu/trunk/rtl/peripherals/
9 This checkin is the result of a watchdog timer test, and everything it took
to get the watchdog timer working. The timer function was simplified,
although it now uses a touch more resources--being able to count down 31
bits instead of 30. The parser was modified, since it couldn't handle
storing to register plus offsets like it was supposed to be able to. The
testbench, zippy_tb, was modified to accept an assembled machine code file
such as I might place on a board to test it.

Lots of work to get it working.

Looking at the files below, it looks like I'll need a second check in to check
in the watchdog timer test itself.
dgisselq 2532d 01h /zipcpu/trunk/rtl/peripherals/
2 An initial load. No promises of what works or not, but this is where the
project is at.
dgisselq 2533d 02h /zipcpu/trunk/rtl/peripherals/

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