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[/] [zipcpu/] [trunk/] [rtl/] [peripherals/] [icontrol.v] - Rev 209

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209 8b bytes, + formal verification throughout + dcache dgisselq 987d 03h /zipcpu/trunk/rtl/peripherals/icontrol.v
201 RTL files for the 8-bit capable ZipCPU. dgisselq 1726d 12h /zipcpu/trunk/rtl/peripherals/icontrol.v
69 This implements the "new Instruction Set" architecture for the Zip CPU. It's
a massive change set, that touches just about everything but probably not
enough of everything. Please see the spec.pdf for a description of this
new architecture.
dgisselq 2169d 14h /zipcpu/trunk/rtl/peripherals/icontrol.v
2 An initial load. No promises of what works or not, but this is where the
project is at.
dgisselq 2318d 08h /zipcpu/trunk/rtl/peripherals/icontrol.v

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