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[/] [zipcpu/] [trunk/] [rtl/] [zipbones.v] - Rev 38

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38 A couple of quick updates:

- The Zip CPU now supports pipelined memory access at one clock per
instruction (assuming all the instructions are in the cache)
- There is now a 'zipbones' module to build a Zip System without peripherals.
Any peripherals would then need to be external to the CPU.
- Some bug fixes.

Documentation changes coming shortly.
dgisselq 2510d 11h /zipcpu/trunk/rtl/zipbones.v

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