URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

[/] [zipcpu/] [trunk/] [rtl/] [zipbones.v] - Rev 48

Rev	Log message	Author	Age	Path
48	Files added/updated to get Dhrystone benchmark to work. Several fixes to the CPU in the process, 'cause it wasn't working. Stall-less ALU ops now work better, to include grabbing the memory result as it comes out of the memory unit and placing it straight into either ALU or memory unit for the next instruction.	dgisselq	3121d 20h	/zipcpu/trunk/rtl/zipbones.v
38	A couple of quick updates: - The Zip CPU now supports pipelined memory access at one clock per instruction (assuming all the instructions are in the cache) - There is now a 'zipbones' module to build a Zip System without peripherals. Any peripherals would then need to be external to the CPU. - Some bug fixes. Documentation changes coming shortly.	dgisselq	3125d 01h	/zipcpu/trunk/rtl/zipbones.v