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[/] [zipcpu/] [trunk/] [sw/] [zasm/] [zopcodes.h] - Rev 137

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89 Minor changes, to include making default branching an ADD.[condition] X,PC
instruction, rather than allowing both MOV X(PC),PC and ADD X,PC instructions.

Further zopcodes.cpp contains several bug fixes.
dgisselq 2981d 17h /zipcpu/trunk/sw/zasm/zopcodes.h
70 Updated the assembler support files, zopcodes in particular, to handle
the disassembly of the new very long instruction word codes.
dgisselq 3012d 19h /zipcpu/trunk/sw/zasm/zopcodes.h
69 This implements the "new Instruction Set" architecture for the Zip CPU. It's
a massive change set, that touches just about everything but probably not
enough of everything. Please see the spec.pdf for a description of this
new architecture.
dgisselq 3018d 23h /zipcpu/trunk/sw/zasm/zopcodes.h
13 Finally! The beginnings of the new assembler. It's not really polished yet,
and it is quite clunky, but it works!! (Lots of bugs and features left to
fix/implement: #include, #define macro(), #line tracking through the
preprocessor, a means of finding include files (and the preprocessor!) and
more. But, as a beginning, the basics are functinoal.
dgisselq 3151d 04h /zipcpu/trunk/sw/zasm/zopcodes.h
2 An initial load. No promises of what works or not, but this is where the
project is at.
dgisselq 3167d 18h /zipcpu/trunk/sw/zasm/zopcodes.h

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