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[/] [zipcpu] - Rev 184

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184 Adjusted the illegal instruction option documentation. dgisselq 2152d 01h /zipcpu
183 Cleaned up the system so that !CYC implies !STB as well. dgisselq 2152d 01h /zipcpu
182 Bug fix for fast memories. This now works for memories with single cycle
latencies.
dgisselq 2152d 01h /zipcpu
181 Adjusted the wishbone logic to include our wishbone simplification that if
CYC is ever low, STB must be low as well.
dgisselq 2152d 01h /zipcpu
180 Cleaned up the stall logic--made it independent of whether or not we are
designed to be alternating or not.
dgisselq 2152d 01h /zipcpu
179 Lots of changes, most (all?) of them to the non-pipelined core. The resulting
core is now about 100-120 LUTs smaller when not-pipelined, and yet maintains
the pipelined logic when necessary.
dgisselq 2152d 01h /zipcpu
178 Rewrote the parameter controlled logic to be just that: perameter controller,
rather than depending upon generics. The result reduces our area by a couple
LUTs.
dgisselq 2152d 01h /zipcpu
177 Fixed the illegal address logic to be more precise. dgisselq 2152d 01h /zipcpu
176 Switched from distributed to block RAM, and adjusted the logic to help
timing closure. The resulting core will build in designs up to 200MHz in
speed.
dgisselq 2152d 01h /zipcpu
175 Fixed the carry bit for logical shifts: it is the last bit shifted out of the
register. 0x80000000>>32 yields a 0 with carry set. Anything logically
shifted by a number greater than thirty two clears carry and register.
dgisselq 2152d 01h /zipcpu
174 Simplified the divide to improve timing performance. dgisselq 2152d 02h /zipcpu
173 Adjusted the pdfinfo field, to accommodate Google's bot. dgisselq 2152d 02h /zipcpu
172 Added a test to see if the compiler properly handles a large number of
arguments. Further, the sibcall enabled compiler now correcly makes a
sibcall from the end of txreg().
dgisselq 2152d 02h /zipcpu
171 This fixes the problem whereby the ZipCPU didn't properly access more than
5 word-sized function parameters.
dgisselq 2154d 07h /zipcpu
170 Minor updates to the orconf.pdf pre-conference slide. (Added the 'to be
revealed' line.
dgisselq 2164d 01h /zipcpu
169 Added details of LM32 to the (pre) ORConf survey slide in trunk/doc. dgisselq 2200d 01h /zipcpu
168 An updated version of the intensive CPU test. This one runs from C, and
requires a UART port and a PIC, but can run quite successfully on multiple
SoCs that have been built with the ZipCPU internal to them.
dgisselq 2213d 01h /zipcpu
167 Updated the spec to reflect changes in the CC register: the user break
flag, and the ability to command a clearing of the instruction cache.
dgisselq 2213d 01h /zipcpu
166 Bugfix version. This fixes a problem whereby function addresses with offsets
were not properly calculated, together with properly setting up pcrelative
offsets when using the move function together with a label.
dgisselq 2213d 05h /zipcpu
165 Added a test to make certain that the arithmetic right shift was properly
propagating the high order bit. (The test works under verilator, but didn't
initially work in Xilinx -- thus a difference between the two.)
dgisselq 2213d 05h /zipcpu

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