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[/] [zipcpu] - Rev 190

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Rev	Log message	Author	Age	Path
170	Minor updates to the orconf.pdf pre-conference slide. (Added the 'to be revealed' line.	dgisselq	2784d 20h	/zipcpu
169	Added details of LM32 to the (pre) ORConf survey slide in trunk/doc.	dgisselq	2820d 20h	/zipcpu
168	An updated version of the intensive CPU test. This one runs from C, and requires a UART port and a PIC, but can run quite successfully on multiple SoCs that have been built with the ZipCPU internal to them.	dgisselq	2833d 20h	/zipcpu
167	Updated the spec to reflect changes in the CC register: the user break flag, and the ability to command a clearing of the instruction cache.	dgisselq	2833d 20h	/zipcpu
166	Bugfix version. This fixes a problem whereby function addresses with offsets were not properly calculated, together with properly setting up pcrelative offsets when using the move function together with a label.	dgisselq	2834d 00h	/zipcpu
165	Added a test to make certain that the arithmetic right shift was properly propagating the high order bit. (The test works under verilator, but didn't initially work in Xilinx -- thus a difference between the two.)	dgisselq	2834d 00h	/zipcpu
164	Updated with inputs from Hellwig Geisse regarding the details of the ECO32 CPU.	dgisselq	2842d 01h	/zipcpu
163	Trimmed OR1K instruction set down from 219 instructions, to the minimum number of 48. Thanks to Olof for helping identify the minimal set!	dgisselq	2850d 03h	/zipcpu
162	Noted 64-bit integers are by extension, as are vector instructions.	dgisselq	2850d 04h	/zipcpu
161	Initial version of the ORConf slides, showing only the initial CPU survey.	dgisselq	2850d 04h	/zipcpu

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