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Rev Log message Author Age Path
164 Updated with inputs from Hellwig Geisse regarding the details of the ECO32
CPU.
dgisselq 2820d 05h /
163 Trimmed OR1K instruction set down from 219 instructions, to the minimum number
of 48. Thanks to Olof for helping identify the minimal set!
dgisselq 2828d 07h /
162 Noted 64-bit integers are by extension, as are vector instructions. dgisselq 2828d 08h /
161 Initial version of the ORConf slides, showing only the initial CPU survey. dgisselq 2828d 08h /
160 Logic updates, and bug fix corrections to bring this in line with the current
XuLA2-LX25 SoC version. (i.e., the XuLA version was debugged and improved,
this update pushes those improvements to the mainline.)
dgisselq 2843d 19h /
159 Now supports building a simulator that can load ELF files, such as GCC and/or
binutils will produce.
dgisselq 2843d 19h /
158 Now automatically builds the toolchain by default. dgisselq 2843d 19h /
157 Added the divide unit to the list of ZipCPU dependencies. dgisselq 2843d 19h /
156 Fixed a compiler warning for an unused result. dgisselq 2843d 19h /
155 Improved debug trace quality, for finding bugs after the fact. dgisselq 2843d 19h /

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