Subversion Repositories zipcpu

[/] - Rev 209


Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
209 8b bytes, + formal verification throughout + dcache dgisselq 1165d 16h /
208 Add install and readme files, updated testb to capture initial variable status in Verilator dgisselq 1886d 03h /
207 Updated the ELF support, and divide test-bench. dgisselq 1886d 03h /
206 Updated assembler, fixes several bugs, adds better bug detection and reporting (fixes some segfaults on bugs) dgisselq 1886d 03h /
205 Updating core to current/best version, to include dblfetch support and full CIS support dgisselq 1886d 03h /
204 Added the two simulators back into the SVN repository dgisselq 1904d 23h /
203 Removed the (now unused) old GCC compiler, v5.3.0 dgisselq 1904d 23h /
202 Additional ZipCPU changes associated w 8b upgrade dgisselq 1905d 00h /
201 RTL files for the 8-bit capable ZipCPU. dgisselq 1905d 01h /
200 Lots of GCC bugs fixed, some new features added, longs should work now. The
build scripts have also been updated and simplified.
dgisselq 2004d 07h /
199 Massive specification rewrite, brings it up to date with the current ZipCPU
state. This does not reflect any major change to the CPU.
dgisselq 2029d 20h /
198 Added a copyright notice. dgisselq 2031d 01h /
197 Added a new multiply testbench. Other changes were necessary to follow. dgisselq 2031d 01h /
196 Updated internal documentation. dgisselq 2031d 01h /
195 Adds a new mode that can handle a delayed stall signal. dgisselq 2031d 01h /
194 Cleaned up some parameters, trying to create more consistency. dgisselq 2031d 01h /
193 These changes make it so the ALU multiplies pass a test-bench. dgisselq 2031d 01h /
192 Fixed a bug with constant alignment in the assembler. dgisselq 2031d 01h /
191 Updated toolchain, more information on the example debugger. dgisselq 2046d 04h /
190 Added the copyright statement back in. dgisselq 2047d 20h /
189 Final, as delivered, ORCONF slides. dgisselq 2047d 20h /
188 Adjusted the opcodes to match the binutils port: added RTN instructions, and
allowed BREAK instructions to include an immediate--to be interpreted by the
dgisselq 2079d 22h /
187 Updated to match changed register definitions within the core. dgisselq 2079d 22h /
186 Now allows profile dumping for ELF executables. dgisselq 2079d 22h /
185 Now includes the proper flags for building with ELF executable file support. dgisselq 2079d 22h /
184 Adjusted the illegal instruction option documentation. dgisselq 2079d 23h /
183 Cleaned up the system so that !CYC implies !STB as well. dgisselq 2079d 23h /
182 Bug fix for fast memories. This now works for memories with single cycle
dgisselq 2079d 23h /
181 Adjusted the wishbone logic to include our wishbone simplification that if
CYC is ever low, STB must be low as well.
dgisselq 2079d 23h /
180 Cleaned up the stall logic--made it independent of whether or not we are
designed to be alternating or not.
dgisselq 2079d 23h /

powered by: WebSVN 2.1.0

© copyright 1999-2022, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.